AXIOMTEK DASP-52282, Руководство пользователя

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DASP-52282 Card User’s Manual
Theorem of Operation
25
C h a p t e r 3
Theorem of Operation
DASP-52282 is a high performance PCI interface multi-function
data acquisition board. To facilitate high speed data acquisition
and data transfer, a series of hardware and software mechanism
has been designed and implemented for DASP-52282. To
synchronize external event and data acquisition, a series of
external trigger mechanism is provided. To guarantee the
gapless data acquisition, a hardware/software level double
buffering and a hardware level automatic channel scanning is
supported. The theorem of these operations is described in the
following sections. Please refer to the software manual of
DASP-52282 for the details and practices of them.
3.1 Overview of DASP-52282 System
Architecture and Operation
The system block diagram of DASP-52282 is depicted as in
following figure. A PCI interface to host is constructed with a PCI
bridge and a 33MHz bus clock is used to drive it. In the local bus
site, 5 major functions of DASP-52282 have been implemented,
include the AD circuits, the DA circuits, the DIO circuits, the
internal control logical circuits and a FIFO buffer that provided the
hardware level data buffering for double buffering mechanism of
DASP-52282.
PCI
Bridge
PC
I BU
S
Loc
al
B
U
S
RT
Register
FIFO
PGA M ultiplexer
IRQ
Logic
Transfer
Logic
Contrller
Convert
Logic
Contrller
Gain
Select
Channel
Select
S oftware
Trigger
16 bits
D I/O
2 Channel
12 bits DAC
16/8 to 1
A/D
CH0 ~ CH15
EXT. Trig
D/I 0 ~ 15
D/O 0 ~ 15
D/A
CH0, CH1
EOC
FIFO HF
..
.
..
.
12 bits
ADC
Timer
Counter 0
Timer
Counter 1
Timer
Counter 2
8M Hz
OS C
EXT. CLK
OUT 0
Pacer
Tick
Middle
Trigger
Counter
System Block Diagram of DASP-52282