DASP-52282 Card User’s Manual
Registry Structure and Format
38
4.2 I/O Register Map
4.2.1
Digital Input Buffer Register
Read (Base A Offset 0x00-01)
D7
D6
D5
D4
D3
D2
D1
D0
Digital Input Low Byte (D0-D7)
D15
D14
D13
D12
D11
D10
D9
D8
Digital Input High Byte (D8-D15)
4.2.2
Digital Output Latch Register
Write (Base A Offset 0x00-01)
D7
D6
D5
D4
D3
D2
D1
D0
Digital Output Low Byte (D0-D7)
D15
D14
D13
D12
D11
D10
D9
D8
Digital Output High Byte (D8-D15)
4.2.3
General Status Buffer Register
Read (Base A Offset 0x02-03)
D7
D6
D5
D4
D3
D2
D1
D0
EnDAC
Diff/SE MidEnd
ExtPulse
PReady
FF
HF
EF
D15
D14
D13
D12
D11
D10
D9
D8
CMDCRL
SetINT OUT0
ModSel2 ModSel1 ModSel0
Handshak
CMDOK
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