AVT MAGIC ISDN, Описание аппаратуры

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PA G E 2 7
S Y S T E M D E S C R I P T I O N
2.5 The ‘Layer II/III Audio Codec ’
The Audio Codec plug-in unit enables the transmission of audio signals at low
bit rates, as is required for ISDN, for example. A reduction by a factor of 11 for
Layer III and by a factor of 6 for Layer II is achieved without any loss in quality.
The encoding is in accordance with the ISO/IEC 11172-3 standard as well as
the DAB ETS300401 standard.
Besides the audio channel, there is an additional data channel with a maxi-
mum data rate of 9.6-kBaud and 38.4-kBaud for DAB, which can be used to
transmit program-accompanying information, for example.
A digital, professional AES/EBU interface has been implimented as input and
output for the audio signal.
FIGURE 2.7 shows the block diagram for this unit. The
'PEQFGT
is implimented
with four signal processors whereas the
&GEQFGT
uses a single signal proces-
sor. On the basis of this relatively high processing power, in general, future co-
ding algoriths can be implimented.
The controlling element of this unit is the
*QUV RTQEGUUQT
. This microcontroller
loads the software for the Codec from the Flash-Eproms, monitors the Codec
and configures it. Under special control registers (De-emphasis, Mux, Level)
the analogue card is likewise controlled.
The clock can be provided in two ways: synchronous with the network clock
(only 48-kHz sampling frequency) or asynchronous with the network clock
using a
8%1
. In the second case, a quasi-synchronous procedure is provided
by a control algorithm in the Decoder.
The Audio data signals can be provided to the codec either from the Analogue
card or the
#'5'$7
interface.
The data exchange with the interface unit is over the
'ZVGPUKQP$WU
. Besides the
data and clock signals (RXD, TXD, X21_CLK, Clk_Syn) the data request si-
gnals (TXD_V, RXD_v) are still required as well as a bi-directional communi-
cations channel (XD, XC).
FIGURE 2.7 BLOCK DIAGRAM OF THE LAYER II/III AUDIO CODEC
Encoder
Layer II/III
Decoder
Layer II/III
V.24
TTL
V.11
TTL
V.11
TTL
V.11
TTL
V.24
TTL
V.11
TTL
UART
PCB-Address
VCO
Clock Mux
Host
Control
AES/
EBU
AES/
EBU
Select Sampl. Clk
RXD
Dig. Aud. Data
Deemph.
Mux
Level
Sampl. Clk (asyn.)
RTS
TXD
TXD_V
RXD_V
X21_Clk
Clk_Syn
RXD
TXD
XD
XC
Sampl. Clk (syn.)
Encoded Audio Data
Transmit Clk
AES/EBU Clk
Audio In
Audio Out
Data to D/A-Converter
Data from A/D-Converter
Hostbus
Hostbus
Hostbus
Add. Data
Add. Data
Ext. Bus
Ext. Bus
Ext. Bus
Ext. Bus
Dig. Aud. Data
Encoded Audio Data