Industrial Managed
Ethernet Switch – EH9711
User Manual
Page
105
of
223
Table 2.70 Description of Clock Source Nomination and State under SyncE
Label
Description
Factory
Default
Clock Source
This is the instance number of the clock source. This has to be referenced when selecting
'Manual' Mode
-
Nominated
When a clock source is nominated, the clock output from the related PHY (Port) is
enabled against the clock controller. This makes it available as a possible source in the
clock selection process. If it is supported by the actual HW configuration, The Station
clock input can be nominated as a Clock Source.
Unclicked
Port
In this dropdown box, the ports that are possible to select for this clock source, is
presented. The station clock input is indicated by a port name = 'S-CLK'.
-
Priority
The priority for this clock source. Lowest number (0) is the highest priority. If two clock
sources have the same priority, the lowest clock source number gets the highest priority
in the clock selection process.
0
SSM Overwrite
A selectable clock source Quality Level (QL) to overwrite any QL received in a SSM. If
QL is not Received in an SSM (SSM is not enabled on this port), the SSM Overwrite QL
is used as if received. The SSM Overwrite can be set to QL_NONE, indicating that the
clock source is without any know quality (Lowest compared to clock source with known
quality)
Disabled
Hold Off
The Hold Off timer value. Active loss of clock Source will be delayed the selected
amount of time. The clock selector will not change clock source if the loss of clock
condition is cleared within this time.
Disabled
ANEG Mode
This is relevant for 1000BaseT ports only. In order to recover clock from port it must be
negotiated to 'Slave' mode. In order to distribute clock, the port must be negotiated to
'Master' mode.
This different ANEG modes can be activated on a Clock Source port:
Prefer Slave:
The Port will be negotiated to 'Slave' mode if possible.
Prefer Master:
The Port will be negotiated to 'Master' mode if possible.
Forced Slave:
The Port will be forced to 'Slave' mode.
The selected port in 'Locked' state will always be negotiated to 'Slave' if possible.
None
LOCS
Signal is lost on this clock source.
-
SSM
If SSM is enabled and not received properly. Type of SSM fail will be indicated in the
'Rx SSM' field
-
WTR
Wait to Restore timer is active.
-
Clear WTR
Clears the WTR timer and makes this clock source available to the clock selection
process.
None
For
Clock Selection Mode and State
, the Clock Selector is only in one instance which is the one who selects between the
nominated clock sources. Table 2.71 summarizes the descriptions of parameters of
Clock Source Nomination and State
under SyncE.
Table 2.71 Description of Clock Selection Mode and State under SyncE
Label
Description
Factory
Default
Mode
The definition of the 'best' clock source is firstly the one with the highest (QL) and
secondly (the ones with equal QL) the highest priority.
Clock Selector can be in different modes:
Manual:
Clock selector will select the clock source stated in Source (see below). If
this manually selected clock source is failing, the clock selector will go into holdover
state.
Manual to Selected:
Same as Manual mode where the pt. selected clock source will
become Source.
Auto NonRevertive:
Clock Selection of the best clock source is only done when the
selected clock fails.
Auto Revertive:
Clock Selection of the best clock source is constantly done.
Force Hold Over:
Clock Selector is forced to Hold Over State.
Auto
Revertive
