Artesyn Embedded Technology SharpStreamer Mini PCIE-7205, Инструкция по установке и использованию

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Functional Description
SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)
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3.4.1 Intel i5-5350U Broadwell Processor
The Broadwell processor is the intended processor for the production of PCIE-7205 card.
3.4.2 Clock Distribution
Clocking for each MCP complex consists of two crystals. One 24 Mhz crystal to drive all the
main buses and a 32.768 Khz crystal to drive the real time clock.
The PCIe differential clock from the PCIe gold fingers connector goes to the i350 dual Gigabit
Ethernet controller. This clock source comes from the server in which the card is inserted into.
Each MCP has a dual channel memory, each memory channel provides an 800 Mhz clock to
their respective memory channel.
3.4.3 Reset Structure
The CPLD controls each MCP reset. During power up the CPLD state machine drives the reset
control to each MCP. During an induced reset from the server, the GPIO on the i350 controller
triggers a reset to the CPLD GPIO input, which in turn reset to the selected individual MCP
processor complex through the CPLD GPIO. Both i218 and 82599EN receives the reset from the
PCH platform reset. The following figure shows the internal reset architecture of the PCIE-7205
card.