Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 270
LRCLK
SCLK
DATA
LEFT RIGHT
LSB
left
MSB
left
MSB
right
LSB
left
16 Clock Slots 16 Clock Slots
LSB
right
Figure 94: Timing for I2S Stream in 32-bit Mode
LRCLK
SCLK
DATA
LEFT RIGHT
LSB MSB MSB LSB
16 Clock Slots 16 Clock Slots
Figure 95: Timing for I2S Stream in Left or Right-Justified and 32-bit Modes
6.11.2.2. SPDIF Audio
The ADV8003 can receive two channel LPCM or encoded multichannel audio up to a 192 kHz sampling rate via the SPDIF input
interface. The detected sampling frequency for the SPDIF input stream can be read via the
spdif_sf[3:0] field.
It is possible to set the sampling audio sampling frequency of the input SPDIF stream. This is done by setting
audio_sampling_freq_sel to
1. When audio_sampling_freq_sel is set to 1, the sampling frequency used to determine the pixel repetition factor (refer to Section 6.11.1 )
is not extracted from the input SPDIF stream and must be programmed in the i2s_sf[3:0] field. Note that the sampling frequency that is
used in the Audio Sample packets sent to the downstream sink can be read from the spdif_sf[3:0] field.
The ADV8003 is capable of accepting SPDIF with or without an audio master clock input to through the input pin MCLK. When the
ADV8003 does not receive an audio master clock, the ADV8003 uses the bit clock input via the SCLK pin to internally generate an audio
master clock and determine the CTS value.
spdif_sf[3:0]
, TX2 Main Map, Address 0xF404[7:4] (Read Only)
This signal is used to readback the audio sampling frequency from the SPDIF channel.