Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 117
2.2.5.3. Single DDR2 Memory Configuration
If using a single DDR2 memory, the number of field buffers must be reduced from seven (default) to four when performing de-interlacing
and scaling on 720p, 1080i and 1080p inputs. This is achieved by enabling intra field interpolation and setting
(
pvsp_ex_mem_data_format[1:0] ) to indicate 16-bit 4:2:2. Next pvsp_frc_low_latency_mode must be enabled. Finally, the field buffers
addresses in DDR2 must be reassigned as follows:
0xE800[31:0] (
pvsp_fieldbuffer0_addr[31:0] ) = 5184000
0xE804[31:0] ( pvsp_fieldbuffer1_addr[31:0] ) = 9331200
0xE808[31:0] ( pvsp_fieldbuffer2_addr[31:0] ) = 13478400
0xE80C[31:0] ( pvsp_fieldbuffer3_addr[31:0]
)
= 17625600
0xE810[31:0] ( pvsp_fieldbuffer4_addr[31:0]
)
= 21772800
0xE814[31:0] ( pvsp_fieldbuffer5_addr[31:0] ) = 25920000
0xE889[31:0] ( pvsp_fieldbuffer6_addr[31:0] ) = 27578880
2.2.5.4. DDR2 Loopback Test
The ADV8003 features a DDR2 loopback test block to allow testing of the ADV8003 DDR2 interface. When the loopback test block is
enabled, it controls the commands sent to the DDR2 controller of the ADV8003 and generates pseudo random data and addresses using a
defined protocol.
The controller first writes a programmable number of random 32-bit words to the external memory. The same number of reads are then
performed from the written addresses. The readback is compared with the pseudo random data generated to check if there are any errors.
The results are available via I
2 C readback.
DDR2
Controller
Loopback
Test Logic
Phy
512Mb x16
External
DDR2 Mem
512M x16
External
DDR2 Mem
32-bit data
32-bit data
16-bit data
16-bit data
address
control
address
control
Figure 43: DDR2 Loopback Test Architecture
A two memory DDR2 loopback test is initialized and started via the following writes:
1A 1A5B 22 ; Recommended Write
1A 1A5F 00 ; Recommended Write
1A 1A61 06 ; Recommended Write
1A 1AA0 13 ; Recommended Write
1A 1AA1 01 ; Recommended Write
1A 1AA2 25 ; Recommended Write
1A 1AA3 1D ; Recommended Write
1A 1AA4 81 ; Recommended Write
1A 1AA5 81 ; Recommended Write
1A 1AA7 53 ; Recommended Write