Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 259
The ADV8003 transmits the GMP data starting 400 pixel clock cycles after the leading edge of VSync. In order to avoid corrupting the
GMP data during transmission, it is recommended that the user synchronizes all I
2
C writes to the GMP registers so that the write begins
512 pixel clock cycles after the VSync leading edge. The VSync interrupt of the ADV8003 should be used to synchronize this timing.
Figure 88 illustrates this timing requirement.
gm_pkt_en , TX2 Main Map, Address 0xF440[2]
This bit is used to enable the Gamut Metadata Packet.
Function
gm_pkt_en Description
0  Disabled
1 Enabled
Figure 88: I 2 C Write Timing if GMP Data
Table 57: Gamut Metadata Packet Configuration Registers
Packet Map
Address Access Type Field Name Default Value Byte Name1
0xF2A0 R/W gmp_hb0[7:0] 0b00000000 Header Byte 0
0xF2A1 R/W gmp_hb1[7:0] 0b00000000 Header Byte 1
0xF2A2 R/W gmp_hb2[7:0] 0b00000000 Header Byte 2
0xF2A3 R/W gmp_pb0[7:0] 0b00000000 Data Byte 0
0xF2A4 R/W gmp_pb1[7:0] 0b00000000 Data Byte 1
0xF2A5 R/W gmp_pb2[7:0] 0b00000000 Data Byte 2
0xF2A6 R/W gmp_pb3[7:0] 0b00000000 Data Byte 3
0xF2A7 R/W gmp_pb4[7:0] 0b00000000 Data Byte 4
0xF2A8 R/W gmp_pb5[7:0] 0b00000000 Data Byte 5
0xF2A9 R/W gmp_pb6[7:0] 0b00000000 Data Byte 6
0xF2AA R/W gmp_pb7[7:0] 0b00000000 Data Byte 7
0xF2AB R/W gmp_pb8[7:0] 0b00000000 Data Byte 8
0xF2AC R/W gmp_pb9[7:0] 0b00000000 Data Byte 9
0xF2AD R/W gmp_pb10[7:0] 0b00000000 Data Byte 10
0xF2AE R/W gmp_pb11[7:0] 0b00000000 Data Byte 11
0xF2AF R/W gmp_pb12[7:0] 0b00000000 Data Byte 12
Falling edge of last DE of
last field
Rising edge of first DE of
next field
VSync
400 pixel
clocks
GMP sending
window
Initiate I2C
change after 512
clocks 112 pixel
clocks