Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 228
Function
filt_5v_det_timer[6:0] Description
1011000  Approximately 4.2us
xxxxxxx Time duration of +5 V deglitch filter. The unit of this parameter is 2 clock cycles of the ring
oscillator (~ 47ns)
dis_cable_det_rst , HDMI RX Map, Address 0xE248[6]
This bit disables the reset effects of cable detection. It should be set to 1 if the +5 V pins are unused and left unconnected.
Function
dis_cable_det_rst Description
0  Resets the HDMI section if the 5 V input pin is inactive
1 Do not use the 5 V input pins as reset signal for the HDMI section
5.2. TMDS CLOCK ACTIVITY DETECTION
The ADV8003 Serial Video Rx provides circuitry to monitor TMDS clock activity and also the type of data on the Rx input lines. System
software can poll these registers and configure the ADV8003 as required.
rb_rx_tmds_clk_det and tmds_pll_locked can be used to
determine if there is a valid clock on the TMDS clock input and if the Serial Video Rx has locked to this. If both of these are true,
rx_hdmi_mode can be used to indicate the video data that is available on the Serial Video Rx, either DVI data or HDMI data.
rx_hdmi_mode , HDMI RX Map, Address 0xE205[7] (Read Only)
This bit is a readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream.
Function
rx_hdmi_mode Description
0  DVI mode detected
1 HDMI mode detected
rb_rx_tmds_clk_det , IO Map, Address 0x1ADF[3] (Read Only)
This bit is used to indicate if there is a clock on the HDMI RX input lines.
Function
rb_rx_tmds_clk_det Description
0  No TMDS clock detected on HDMI rx input lines
1 TMDS clock detected on HDMI rx input lines
tmds_pll_locked
, HDMI RX Map, Address 0xE204[1] (Read Only)
This is a readback bit to indicate if the TMDS PLL is locked to the TMDS clock input of the selected HDMI port.
Function
tmds_pll_locked Description
0  TMDS PLL not locked
1 TMDS PLL is locked to the TMDS clock input of the selected HDMI port
Note:
The tmds_pll_locked flag should be considered valid if a TMDS clock is input on the Serial Video Rx.