Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 224
This bit is used to select the SPI slave clock polarity.
Function
spi_slave_cpol Description
0 Idle state, clock is low
1  Idle state, clock is high
spi_slave_cpha
, IO Map,
Address 0x1A14[2]
This bit is used to select the SPI slave clock phase.
Function
spi_slave_cpha Description
0 Negedge used
1  Posedge used
As can be seen from
Figure 80 , the LSB bit of the device address sets whether the access is read or write.
The SPI subaddress is an 8-bit field and the data is also 8 bits wide with MSB sent first and LSB last.
The SPI slave readback has both delay mode and no delay mode, and it is controlled by the following SPI register.
slave_delay_mode , SPI Device Address 0x0A, Address 0x85[0]
SPI slave read data MISO1 output delay mode.
Function
slave_delay_mode Description
0 No delay
1  Delay 8 clocks (8 bits dummy data)
In no delay mode, counting from the last rising edge of SCK1 (send subaddress) to the first falling edge of SCK1 (send out MISO1), there
are about 10 system clock delays. Assuming the SCK1 is 50% duty cycle, only when SCK1 is slower than system clock/20 = 162 MHz/20 =
8.1 MHz, can no delay mode work normally.
If SCK1 is slower than 6 MHz, no delay mode can be set.
The ADV8003 features an analog antiglitch used to reject glitches on SCK1 (SPI slave). There are three modes of operation of this filter:
bypass, 2 ns glitch rejection, and 5ns glitch rejection. The 2 ns glitch rejection mode should be used for clock frequencies between 10MHz
and 40 MHz. The 5 ns glitch rejection mode should be used for clock frequencies of less than 10 MHz.
spi_filter_en , IO Map, Address 0x1A2C[7]
This bit is used to enable the SPI anti glitch filter.
Function
spi_filter_en Description
0  Anti glitch filter disable
1 Anti glitch filter enable
spi_filter_sel , IO Map, Address 0x1A2C[6]
This bit is used to select the response of the SPI anti glitch filter.