Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 361
To find C1 and C2, use the following formula:
C1
=
C2
=
2(C
load
– C
stray
)
-
C
pg
where
C
stray
is usually 2 to 3 pF, depending on board traces and C
pg
(pin-to-ground-capacitance) is 4 pF for the ADV8003.
Example:
C
load
= 30 pF, C1 = 50 pF, C2 = 50 pF (in this case, 47 pF is the nearest real-life cap value to 50 pF)
Encoder Component Placement
External component placement must be carefully considered – they should be kept as far away from noisy circuits as possible, as close to
the ADV8003 as possible and preferably on the same layer as the ADV8003. The external loop filter (connected to PVDD3), COMP,
termination resistors, V
REF
, and R
SETx
circuits must all be laid out carefully otherwise noise may couple onto the SD or HD encoder
outputs.
Any external filter and buffer components connected to the encoder analog outputs should be placed close to the ADV8003 to minimize
the possibility of noise cross talk between neighboring circuitry. The encoder analog output traces should be kept as short as possible to
reduce the possibility of any signal integrity issues and to minimize the effect of trace capacitance on output bandwidth.
HDMI Transmitter Component Placement
External component placement must be carefully considered – they should be kept as far away as possible from noisy circuits, as close to
the ADV8003 as possible and preferably on the same layer as the ADV8003. The R_TX1 and R_TX2 resistors and PVDD5 and PVDD6
power supplies must all be carefully laid out otherwise the HDMI transmitter performance, for example, HDMI compliance testing, may
be reduced.
Power Supply Design and Sequencing
The ADV8003 requires only two regulators, one 3.3 V and one 1.8 V. The recommended power supply design is illustrated in Figure 139 .
If using more than one 1.8 V regulator to supply ADV8003, it must be ensured that DVDD_DDR, PVDD_DDR and DVDD are supplied
by the same regulator.
The power-up sequence of the ADV8003 is as follows:
1. Hold RESET and PDN pins low.
2. Bring up the 3.3 V supplies (DVDD_IO, AVDD1, and AVDD2).
3. A delay of a minimum of 20 ms is required from the point in which the 3.3 V reaches its minimum recommended value (that is,
3.14 V) before powering up the 1.8 V supplies.
4. Bring up the 1.8 V supplies (DVDD, CVDD1, PVDD1, PVDD2, PVDD3, AVDD3, DVDD_DDR, and PVDD_DDR). These
should be powered up together, that is, there should be a difference of less than 0.3 V between them.
5. RESET may be pulled high after supplies have been powered up.
6. A complete RESET is recommended after power up. This can be performed by the system microcontroller.