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Chapter 4 Remote Interface Reference
The SCPI Status Registers
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The Standard Event register is cleared when:
• You execute the
*CLS
(clear status) command.
• You query the event register using the
*ESR?
(Event Status register)
command.
For example, 28 (4 + 8 + 16) is returned when you have queried the status of
the Standard Event register, QYE, DDE, and EXE conditions have occurred.
The Standard Event Enable register is cleared when:
• You execute the
*ESE 0
command.
• You turn on the power and have previously configured the power supply
using the
*PSC 1
command.
• The enable register will not be cleared at power-on if you have previously
configured the power supply using the
*PSC 0
command.
For example, you must send the
*ESE 24
(8 + 16) to enable DDE and EXE
bits.
The Status Byte Register
The Status Byte summary register reports conditions from the other status
registers. Query data that is waiting in the power supply's output buffer is
immediately reported through the “Message Available” bit (bit 4) of Status
Byte register. Bits in the summary register are not latched. Clearing an event
register will clear the corresponding bits in the Status Byte summary
register. Reading all messages in the output buffer, including any pending
queries, will clear the message available bit.
Table 4-4. Bit Definitions - Status Byte Summary Register
Bit
Decimal
Value
Definition
0-2 Not Used 0 Always set to 0.
3 QUES 8
One or more bits are set in the questionable status
register (bits must be “enabled” in the enable register).
4 MAV 16 Data is available in the power supply output buffer.
5 ESB 32
One or more bits are set in the standard event register
(bits must be “enabled” in the enable register).
6 RQS 64 The power supply is requesting service (serial poll).
7 Not Used 0 Always set to 0.