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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
The Format Tab
The Format Tab
Under
Format
, you specify the parts of the target system that you
want the logic analyzer to look at. You set up labels to match the buses
of the target system, and set the threshold level for the signals. For a
state measurement
, you also adjust the setup and hold time.
For advanced measurements,
Format
is also where you assign pods
and specify whether to look at channels on the master, slave, or
demultiplexed clock.
Common
Measurement
Controls
“Labels: Mapping Analyzer Channels to Your Target” on page 68
“Setting the Pod Threshold” on page 70
“State Clock Setup/Hold (State only)” on page 71
Advanced
Measurement
Controls
“Assigning Pods to the Analyzers” on page 63
“Clock Modes (State only)” on page 43
“Setting Up the Pod Clock” on page 68
“Pod Selection” on page 69
See Also
“Data On Clocks Display” on page 64
“Activity Indicators” on page 62
“Assigning Bits to a Label” on page 64
“Inserting and Deleting Labels” on page 65
“Turning Labels On and Off” on page 66
“To reorder bits in a label” on page 67
“Importing Netlist and ASCII Files” on page 54
“Label Polarity” on page 66
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