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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
Importing Netlist and ASCII Files
Importing Netlist and ASCII Files
Netlist Files
The Netlist Import feature provides a method for importing busses and
signals from ASCII netlists created by EDA tools. In order for the
feature to work, the device under test must either use the Agilent
E5346A high density adapter or the Agilent Technologies Termination
Adapter. The adapter must be included as a connector in the netlist.
You can create a Netlist file using an EDA tool. When importing a
Netlist file, you can specify which connectors are of interest;
connectors that are not specified will be ignored.
Example
NET'/Bus1(3)'J1-7
Bus1
Four bit bus
(3)
Bit 3
J1-7
Connector J1, pin 7
To Import a Net List
1. Configure the connector names referenced in the Netlist to logic analyzer
pods.
2. Specify the Net List file to import.
3. Verify that Nets were correctly mapped to Labels, Pods, and Channels.
4. Select or create labels to appear in the interface.
Map the Connector Names (see page 60).
Import the Net List File (see page 60)
Verify Net to Label Mapping (see page 61)
Select/Create Interface Labels (see page 62)
ASCII Files
You can create an ASCII file using any Windows, MS-DOS, or UNIX text
editor. The ASCII file should contain bus names, pod/clock numbers,
and channel definitions.
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