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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
The Sampling Tab
Data is collected on a
pod pair
basis, even when labels cross pod
boundaries. It is still displayed on a label basis, however. Because of
this, some pod pairs with less active channels may take longer to fill
memory and the end of the acquisition is delayed. Debugging will be
simpler if you restrict labels to a single pod-pair when using transitional
timing mode.
Each time a transition occurs on any of the assigned bits, all bits of the
pod pair are stored along with a time tag. If transitions are
exceptionally far apart, the timer which generates the time tags may
overflow.
NOTE:
The timer does not generate a warning when it overflows. If the time between
transitions in the display seems too short, it may be due to timer overflow.
“64K Full Channel Transitional 125-MHz Mode” on page 48
“Other Transitional Timing Considerations” on page 49
64K Full Channel Transitional 125-MHz Mode.
The total memory
depth is 64K samples per
channel
.
The analyzer uses half its memory (64K) to store time tags. Because
each pod pair stores transitions at its own rate, you do not have the
option of using a free pod to retain full memory as you have in the state
mode.
Data is sampled for new transitions every 8 ns; this rate cannot be
changed. When a transition on any of the assigned channels is
detected, the data for the entire pod pair is stored.
When a transition is detected after a sample with no detected
transition, two samples are stored. One sample is a "before transition
sample" and the other is an "after transition sample." As long as there
are transitions in the subsequent sample, only one sample is stored.
When the next sample occurs without a transition, the two stored
sample sequences (one before, one after) repeats with the next
detected transition.
Minimum and
Maximum Transitions
Stored
Minimum Transitions Stored
Normally, transitions have not occurred at each sample period. This is
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