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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
The Sampling Tab
Master
Data on all pods assigned to
Master Clk
is strobed into memory when
the status of the clock lines match the clocking arrangement specified
for
Master
in the clock setup.
Slave
Data on a pod designated
Slave Clock
is latched when the status of the
slave clock inputs meet the requirements of the slave clocking
arrangement. Then, followed by a valid master clock, the slave data is
strobed into analyzer memory along with the master data.
If multiple slave clocks occur between master clocks, only the data
latched by the last slave clock prior to a valid master clock is strobed
into analyzer memory.
Latching Slave Data
Demultiplex
The demultiplex mode is used to store two different sets of data that
occur at different times on the same channels. In demultiplex mode,
only one pod of the
pod pair
is used, and that pod is selectable (see
page 69). Channel assignments are displayed as
Pod
and
Slave Pod
.
Assign slave and master data to separate
labels
for easy recognition of
the two sets of data.
Both the master and slave clocks are used in the demultiplex mode.
When the analyzer sees a match between the slave clock input and the
slave clock arrangement, demux slave data is latched. Then, following a
valid master clock, the slave data is strobed into analyzer memory
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