244
MC97F60128
ABOV Semiconductor Co., Ltd.
When the receiver is enabled (RXEn=1), the clock recovery logic tries to find a high-to-low transition on the RXDn line,
the start bit condition. After detecting high to low transition on RXDn line, the clock recovery logic uses samples 8,9
and 10 for normal mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is
considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data
frame. And the data recovery can begin. The synchronization process is repeated for each start bit.
As described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. Data
recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each
incoming bits for normal mode and 8 times for double speed mode and uses sample 8, 9 and 10 to decide data value.
If more than 2 samples have low levels, the received bit is considered to a logic
‘0’ and if more than 2 samples have
high levels, the received bit is considered to a logic
‘1’. The data recovery process is then repeated until a complete
frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note
that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first stop bit, the Receiver is in idle
state and waiting to find start bit.
Figure 11.60
Sampling of Data and Parity Bit (where n = 2,3 and 4)
The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center
values have high level, correct stop bit is detected, else a frame error (FEn) flag is set. After deciding whether the first
stop bit is valid or not, the Receiver goes to idle state and monitors the RXD line to check a valid high to low transition
is detected (start bit detection).
Figure 11.61
Stop Bit Sampling and Next Start Bit Sampling (where n = 2,3 and 4)
RXD
1
2
3
4
5
6
7
8
9
10
11
12
13
STOP 1
1
2
3
4
5
6
7
Sample
(U2Xn = 0)
Sample
(U2Xn = 1)
(A)
(B)
(C)
RXD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
BIT n
1
2
3
4
5
6
7
8
1
Sample
(U2Xn = 0)
Sample
(U2Xn = 1)
Содержание MC97F60128
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