Abov MC97F60128, Руководство пользователя

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13
MC97F60128 ABOV Semiconductor Co., Ltd.
3. Pin assignment
MC97F60128L
(100LQFP-1414)
1
2
2
6
2
7
8
9
15
16
3
4
5
6
7
2
8
2
9
3
0
3
1
3
7
3
8
3
9
4
0
4
1
75
74
68
67
61
60
73
72
71
70
69
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
17
18
24
25
19
20
21
22
23
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
59
58
52
51
57
56
55
54
53
8
9
8
8
8
7
8
1
8
0
7
9
7
8
7
7
7
6
P00/AN0/EINT0/BLNK
P01/AN1/EINT1
P04/AN4/EINT4
P05/AN5/EINT5
P06/AN6/EINT6
P02/AN2/EINT2
P03/AN3/EINT3
RUNFLAG
AVSS
RESETB
LPF
VREG
VSS1
SXIN
SXOUT
VDD1
P17/XOUT
P16/XIN
P07/AN7/EINT7
AVREF
P
6
2
/A
N
8
/E
IN
T
1
7
/T
7
O
P
6
4
/A
N
1
0
/T
X
D
2
P
6
3
/A
N
9
/E
C
7
/D
A
C
P
6
1
/E
IN
T
1
8
/T
8
O
/P
W
M
8
A
A
P
6
0
/S
E
G
0
/P
W
M
8
A
B
P
7
4
/C
O
M
3
P
7
3
/S
E
G
4
/V
L
C
0
/P
W
M
8
C
B
P
7
2
/S
E
G
3
/V
L
C
1
/P
W
M
8
C
A
P
7
1
/S
E
G
2
/V
L
C
2
/P
W
M
8
B
B
P
7
0
/S
E
G
1
/V
L
C
3
/P
W
M
8
B
A
P
6
5
/A
N
1
1
/R
X
D
2
P
7
7
/C
O
M
0
P
7
5
/C
O
M
2
P
7
6
/C
O
M
1
P
8
0
/S
E
G
1
0
P
8
1
/S
E
G
1
1
P
8
5
/S
E
G
1
5
P
8
4
/S
E
G
1
4
P
8
3
/S
E
G
1
3
P
8
2
/S
E
G
1
2
P87/SEG17
P86/SEG16
P40/SEG29/EC0
PB2/SEG28
P52/SEG20/RXD3
P51/SEG19/TXD4
P54/SEG22/SS1
P53/SEG21/TXD3
P56/SEG24/TXD1/SDA1/MOSI1
P55/SEG23/SCK1
P50/SEG18/RXD4
P41/SEG30/EC1
P46/SEG35/BUZO
P45/SEG34/EINT12/T2O/PWM2O
P42/SEG31/EC2
P44/SEG33/EINT11/T1O/PWM1O
P43/SEG32/EINT10/T0O/PWM0O
P31/SEG38/TXD0/SDA0/MOSI0
P30/SEG37/SCK0
P47/SEG36/SS0
P
1
1
/S
E
G
5
9
/E
IN
T
1
4
/T
4
O
/P
W
M
4
O
P
1
0
/S
E
G
5
8
/E
IN
T
1
3
/T
3
O
/P
W
M
3
O
/E
X
T
S
P
2
P
2
7
/C
O
M
7
/S
E
G
5
2
/E
C
4
/E
X
T
S
P
1
P
2
6
/C
O
M
6
/S
E
G
5
1
/E
C
3
/E
X
T
S
P
0
P
2
5
/C
O
M
5
/S
E
G
5
0
/T
R
IG
P
2
4
/C
O
M
4
/S
E
G
4
9
/P
W
M
O
U
T
P
2
3
/S
E
G
4
8
/(
T
3
O
/P
W
M
3
O
/E
X
T
S
P
2
)
P
1
3
/S
E
G
6
1
/E
IN
T
1
6
/T
6
O
/P
W
M
6
O
P
1
2
/S
E
G
6
0
/E
IN
T
1
5
/T
5
O
/P
W
M
5
O
P
1
5
/S
E
G
6
3
/E
IN
T
9
/E
C
6
/
D
S
D
A
P
1
4
/S
E
G
6
2
/E
IN
T
8
/E
C
5
/
D
S
C
L
P
3
6
/S
E
G
4
3
/S
S
2
/C
S
B
2
P
3
5
/S
E
G
4
2
/S
C
K
2
P
2
0
/S
E
G
4
5
/M
O
S
I3
P
3
7
/S
E
G
4
4
/M
IS
O
3
/L
D
A
C
B
3
P
2
2
/S
E
G
4
7
/S
S
3
/C
S
B
3
P
2
1
/S
E
G
4
6
/S
C
K
3
P
3
4
/S
E
G
4
1
/M
O
S
I2
P
3
3
/S
E
G
4
0
/M
IS
O
2
/L
D
A
C
B
2
P
3
2
/S
E
G
3
9
/R
X
D
0
/S
C
L
0
/M
IS
O
0
13
14
10
11
12
63
62
66
65
64
P90/AN12/EINTA
P91/AN13/EINTB
P92/AN14/EINTC
P93/EINTD
P94/EINTE
P57/SEG25/RXD1/SCL1/MISO1
VSS2
VDD2
PB1/SEG27
PB0/SEG26
3
2
3
3
3
4
3
5
3
6
P
A
1
/S
E
G
5
4
/E
IN
T
G
P
A
0
/S
E
G
5
3
/E
IN
T
F
P
A
3
/S
E
G
5
6
/E
IN
T
I
P
A
2
/S
E
G
5
5
/E
IN
T
H
P
A
4
/S
E
G
5
7
/E
IN
T
J
8
6
8
5
8
4
8
3
8
2
P
D
0
/S
E
G
5
P
D
1
/S
E
G
6
P
D
4
/S
E
G
9
P
D
3
/S
E
G
8
P
D
2
/S
E
G
7
NOTE)
1. On On-Chip Debugging, ISP uses P1[5:4] pin as DSDA, DSCL.
2. The pin in parentheses can be configured by software control.
Figure 3.1 MC97F60128L 100LQFP pin assignment