Abov MC97F60128, Руководство пользователя

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MC97F60128 ABOV Semiconductor Co., Ltd.
7.14 UART0/1/2/3/4 Characteristics
(T
A
=-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f
XIN
=11.1MHz)
Parameter Symbol MIN TYP MAX Unit
Serial port clock cycle time t
SCK
1250 t
CPU
x 16 1650 ns
Output data setup to clock rising edge t
S1
590 t
CPU
x 13
–
ns
Clock rising edge to input data valid t
S2
– –
590 ns
Output data hold after clock rising edge t
H1
t
CPU
- 50 t
CPU
–
ns
Input data hold after clock rising edge t
H2
0
– –
ns
Serial port clock High, Low level width t
HIGH
,t
LOW
470 t
CPU
x 8 970 ns
Table 7-15 UART0/1/2/3/4 Characteristics
t
HIGH
t
LOW
t
SCK
Figure 7.3 Waveform for UART0/1/2/3/4 Timing Characteristics
Shift Clock
Data Out D1 D2 D3 D4 D5 D6 D7 D0
Valid Data In Valid Valid Valid Valid Valid Valid Valid
t
SCK
t
S1
t
H1
t
H2
t
S2
Figure 7.4 Timing Waveform for the UART0/1/2/3/4 Module