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Publication No. UGCR12V051E Rev. A.0
Advanced Screen 27
4.4.7
PCI-X Latency Timer
The optimal default is
64 PCI Bus Clocks
.
This feature defines how long a PCI‐X device can keep the PCI‐X bus befo
re another
PCI‐X device takes
over. The timer starts when the device gains bus ownership, and
counts down at the rate of the PCI‐X clock. When the counter reaches
zero, the
PCI‐X
device releases the bus. If no other
PCI‐X
device is waiting for bus ownership, it may
take the bus again and transfer more data.
For better PCI‐X throughput, a longer latency should be used. In addition, time
critical applications may work better with shorter latencies. Customer should
benchmark his system performance to determine
the optimal PCI‐X Latency Timer.
4.4.8
Relaxed Ordering
The optimal default is
Disabled
.
PCI bridges have no way of knowing which transactions are associated between
multiple active devices (e.g. between local PCI bus and CPCI bus).
Enabling this option eliminates unnecessary transaction blocking by allowing
Relaxed Ordering.
4.4.9
Extended Tag
The optimal default is
Disabled
.
A tag is an 8‐bit field generated by each requestor, and it must be unique for all
outstanding requests. The tag field in the request is memorized by the completer and
the same tag is used in the completion.
By default the number of request per device / function is limited to 32, and only
requires 5 bits of the field. Once this bit is set, the entire field is used and the number
of requests is increased to 256.
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