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Publication No. 500-657806-000 Rev. G
Standard Features 33
The slave PIC accepts the CompactPCI interrupts through lines that are defined
by the BIOS. The BIOS defines which interrupt line to utilize depending on which
system requires the use of the line.
2.5 PCI Device Interrupt Map
The PCI bus-based external devices include the PMC sites, Ethernet controller
and the PCI-to-PCI bridge. The default BIOS maps these external devices to the
PCI Interrupt Request (PIRQx) lines of the ICH2. This mapping is illustrated in
and is defined in
The device PCI interrupt lines (INTA through INTH) that are present on each
device cannot be modified.
Table 2-4 PCI Device Interrupt Mapping by the BIOS
DEVICE
COMPONENT
VENDOR ID DEVICE ID
CPU
ADDRESS
MAP ID
SELECT
PCI IRQ
Arbitration
Request
Line
BUS
PCI-to-PCI Bridge Hint HB6
0x3388
0x0020/21*
AD19
INTE, F, G, H
REQ2
2
PMC1
N/A
N/A
N/A
AD17
INTD, A, B, C
REQ3
2
PMC2
N/A
N/A
N/A
AD30
INTC, D, A, B
REQ2
1
Ethernet
Controller
Intel 82546EB**
Intel 82546GB***
0x8086
0x1010
0x1079
AD21
INTA, B
REQ1
2
Host-Hub
Interface Bridge
GMCH
0x8086
0x3580
N/A
N/A
N/A
0
System
Peripheral
GMCH
0x8086
0x3584
N/A
N/A
N/A
0
System
Peripheral
GMCH
0x8086
0x3585
N/A
N/A
N/A
0
Graphics
Controller
GMCH
0x8086
0x3582
N/A
INTA
N/A
0
PCI-LPC Bridge
ICH
0x8086
0x25A1
N/A
N/A
N/A
0
SATA Controller
ICH
0x8086
0x25A3
N/A
INTC
N/A
0
SMBus Controller ICH
0x8086
0x25A4
N/A
INTB
N/A
0
PCI-to-Hub Bridge ICH
0x8086
0x25A0
N/A
N/A
N/A
0
PCI Bridge
ICH
0x8086
0x25AE
N/A
N/A
N/A
0
USB UHCI
ICH
0x8086
0x25A9
N/A
INTA
N/A
0
WDT
ICH
0x8086
0x25AB
N/A
ISA INT9
N/A
0
USB EHCI
ICH
0x8086
0x25AD
N/A
INTH
N/A
0
*Device 20 = INTs E, F, G, H
Device 21 = INT E
**Intel 82546EB is used on non-RoHS version of product (CPCI-7806)
***Intel 82546GB is used on RoHS version of product (CPCI-7806RC)