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Publication No. 500-657806-000 Rev. G
Embedded PC/RTOS Features 39
3.1.4 Transaction Forwarding
• Three primary interface base address configuration registers for
downstream forwarding with size and prefetchable programming for all
three address ranges
• Direct offset address translation for downstream memory and I/O
transactions
• Three secondary interface address ranges for upstream forwarding, with
size and prefetchable programming for all three address ranges
NOTE
Configuration of the Universal Bridge memory and IO register space is selected via the CMOS Setup
Chipset section.
3.2 Watchdog Timer
3.2.1 General
The Watchdog Timer (WDT) supports the following features and functions:
• Selectable prescaler - approximately 1 MHz (1µs to 1s) and approximately
1 kHz (1 ms to 10 min)
• 33 MHz clock (30 ns clock ticks)
• Multiple modes (WDT and free-running)
Free-running mode:
• One stage timer
• Toggles WDT_OUT# after programmable time
WDT Mode:
• Two stage timer (first stage generates interrupt, second stage drives
WDT_OUT# low)
– First stage generates IRQ, SMI or SCI interrupt after programmable time
– Second stage drives WDT_OUT# low or inverts the previous value
– Used only after first timeout occurs
– Status bit preserved in RTC well for possible error detection and
correction
– Drives WDT_TOUT# when OUTPUT is enabled
• Timer may be disabled (default state) or locked (hard reset required to
disable WDT)
• WDT automatic reload of preload value when WDT reload sequence is
performed
3.2.2 Function
The Watchdog Timer provides a resolution that ranges from 1µ sec. to 10 minutes.
The timer uses a 35-bit Down-Counter. The counter is loaded with the value from
the first Preload register. The timer is then enabled and starts counting down. The
time at which the WDT first starts counting down is called the first stage. When
the host fails to reload the WDT before the 35-bit down counter reaches zero, the
WDT generates an internal interrupt. After the interrupt is generated, the WDT