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40 CPCI-7806/CPCI-7806RC Pentium/Celeron M Universal CompactPCI Single Board Computer
Publication No. 500-657806-000 Rev. G
loads the value from the second Preload register into the WDT’s 35-bit Down-
Counter and starts counting down. The WDT is now in the second stage. If the
host fails to reload the WDT before the second timeout, the WDT drives the
WDT_TOUT# pin low and sets the timeout bit (WDT_TIMEOUT). This bit
indicates that the System has become unstable. The WDT_TOUT# pin is held low
until the system is reset or the WDT times out again (depends on TOUT_CNF).
The process of reloading the WDT involves the following sequence of writes:
1. Write 80 to offset BAR1 + 0C.
2. Write 86 to offset BAR1 + 0C.
3. Write 1 to WDT_RELOAD in Reload Register.
The same process is used for setting the values in the preload registers. The only
difference exists in step 3. Instead of writing a 1 to the WDT_RELOAD, write the
desired preload value into the corresponding Preload register. This value is not
loaded into the 35-bit down counter until the next time the WDT re-enters the
stage. For example, when Preload Value 2 is changed, it is not loaded into the
35-bit down counter until the next time the WDT enters the second stage.
Figure 3-1 Watchdog Timer Block Diagram
PCI
Configuration
Registers
Preload Value 1
Preload Value 2
Down-Counter
WDT_TOUT#
(External)
SMI/SCI/IRQ
(Internal)
Reset/Interrupt Control Logic
PCI