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Publication No. 500-657806-000 Rev. G
Embedded PC/RTOS Features 43
The Base Address Register points to several memory mapped registers for the
WDT. It decodes the smallest possible region of 16 Bytes.
Table 3-9 Revision Identification Register (RID)
Offset
08h
Attribute
Read Only
Default Value
00h
Size
8 bit
Lockable
No
Power Well
Core
Table 3-10 Programming Interface Register (PI)
Offset
09h
Attribute
Read Only
Default Value
00h
Size
8 bit
Lockable
No
Power Well
Core
Table 3-11 Sub Class Code Register (SCC)
Offset
0Ah
Attribute
Read Only
Default Value
80h
Size
8 bit
Lockable
No
Power Well
Core
Table 3-12 Base Code Class Register (BCC)
Offset
0Bh
Attribute
Read Only
Default Value
08h
Size
8 bit
Lockable
No
Power Well
Core
Table 3-13 Header Type Register (HEDT)
Offset
0Eh
Attribute
Read Only
Default Value
00h
Size
8 bit
Lockable
No
Power Well
Core
Table 3-14 Base Address Register 1 (BAR1)
Offset
10h
Attribute
Read-Write
Default Value
00000000h
Size
32 bit
Lockable
No
Power Well
Core
Table 3-15 Details of Base Address Register 1 (BAR1)
Bit
Attribute
Description
31:4
R/W
Base Address: These bits are used to determine the size of the memory-
mapped region being requested.
3
RO
Prefetchable: Hard-wired to ‘0’, indicating that this range is not prefetchable.
Read Only