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44 CPCI-7806/CPCI-7806RC Pentium/Celeron M Universal CompactPCI Single Board Computer
Publication No. 500-657806-000 Rev. G
Software (BIOS) will write the value to this register. After that, the value may be
read, but writes to the register will have no effect. The write to this register should
be combined with the write to the SID to create one 32-bit write.
Software (BIOS) will write the value to this register. After that, the value may be
read, but writes to the register will have no effect. The write to this register should
be combined with the write to the SVID to create one 32-bit write.
2:1
RO
Type: Hard-wired to ‘00’, indicating that this range can be mapped anywhere in
32-bit address space. Read Only
0
RO
RTE - Resource Type Indicator: This bit is hard-wired to ‘0’, indicating a
request for memory space. Read Only
Table 3-16 Subsystem Vendor ID (SVID)
Offset
2Ch-2Dh
Attribute
Read, Write Once
Default Value
00h
Size
16 bit
Lockable
No
Power Well
Core
Table 3-17 Subsystem ID (SID)
Offset
2Eh-2Fh
Attribute
Read, Write Once
Default Value
00h
Size
16 bit
Lockable
No
Power Well
Core
Table 3-18 WDT Configuration Register
Offset
60-61h
Attribute
Read-Write
Default Value
00h
Size
16 bit
Lockable
No
Power Well
Core
Table 3-19 Details of WDT Configuration Register
Bit
Attribute
Description
15:6
RO
Reserved
5
R/W
WDT_OUTPUT: Out Enable: This bit indicates whether or not the WDT will toggle the
external WDT_TOUT# pin when the WDT times out.
0 - Enabled (Default)
1 - Disabled
4:3
RO
Reserved
2
R/W
WDT_PRE_SEL: Prescaler Select: The WDT provides two options for prescaling the
main Down Counter. The preload values are loaded into the main down counter right
justified. The prescaler adjusts the starting point of the 35-bit down counter.
0 - The 20-bit Preload Value is loaded into bits 34:15 of the main down counter. The
resulting timer clock is the PCI Clock (33 MHz) divided by 2
15
. The approximate
clock generated is 1 kHz, (1 ms to 10 min). (Default)
1 - The 20-bit Preload Value is loaded into bits 24:5 of the main down counter. The
resulting timer clock is the PCI Clock (33 MHz) divided by 2
5
. The approximate clock
generated is 1 MHz, (1
μ
to 1 sec).
Table 3-15 Details of Base Address Register 1 (BAR1) (Continued)
Bit
Attribute
Description