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34 CPCI-7806/CPCI-7806RC Pentium/Celeron M Universal CompactPCI Single Board Computer
Publication No. 500-657806-000 Rev. G
Figure 2-1 Connections for the PC Interrupt Logic Controller
The PCI-to-PCI Bridge has the capability of generating an NMI via the PCI SERR#
line.
describes the register bits that are used by the NMI. The SERR
interrupt is routed through logic back to the NMI input line on the CPU. The CPU
reads the NMI Status Control register to determine the NMI source (bits set to 1).
After the NMI interrupt routine processes the interrupt, software clears the NMI
status bits by setting the corresponding enable/disable bit to 1. The NMI Enable
and Real-Time Clock register can mask the NMI signal and disable/enable all
NMI sources.
8259 MASTER- PORTS $020-$021
IRQ0
IRQ1
IRQ2
IRQ4
IRQ5
IRQ7
EMBEDDED
INTA
PCI INTERRUPT MAPPER
IRQ6
IRQ3
CPU
INTR
CONNECTIONS
MAPPED BY BIOS
PMC
Site #2
BRIDGE
C
P
C
b
u
s
Timer
Keybd
Com 2
Com 1
Unused Floppy
Control
Interrupt
8-15
Unused
Real-Tm
Clock
Mouse
Math
AT
CompactFlash
Hard Drv
NA
NA
Coproc
PIRQA PIRQB PIRQC PIRQD
IRQ2
INTB
INTC
INTD
8259 SLAVE- PORTS $0A0-$0A1
I/O Controller Hub
ICH
INT
Drive
I
Bus
PCI to PCI
PIRQE
IRQ8
IRQ9
IRQ10
IRQ12
IRQ11
IRQ13
IRQ14
IRQ15
o
m
p
a
c
t
PIRQF PIRQG
PIRQH
PMC
Site #1
INTA
INTB
INTC
INTD
Ethernet
INT
INT
WDT