3. Theory of Operation
34
and 10BaseT transceiver is provided on the ZT 8995-D1. 10BaseT will drive a
maximum cable length of 100 m.
•
Is the ZT 8995 compatible with the WD 8003EB interface?
–
Yes, the two boards are identical for software operation. The same software
driver disk can be used for either board.
–
At the hardware level, the two boards are quite different and the ZT 8995 needs
to be configured specifically for WD 8003EB compatibility (shared RAM mode,
etc.). Unlike the WD 8003EB board, the ZT 8995 also features isolation of the
AUI connector. This feature helps prevent damage to the ZT 8995 from external
cable glitches.
–
Both boards utilize the IEEE
802.3 latching DB15 connector to insure
compatibility with IEEE 802.3 AUI devices.
•
Is the ZT 8995 really STD bus format?
–
The ZT 8995 uses no extensions or porches to implement 10BaseT or Thin
Ethernet interfaces on a standard STD size board.
–
The ZT 8995 requires only one STD slot at .625" centers. Two slots are required
if .500" centers are used.
STD INTERFACE
The ZT 8995 interfaces with the STD bus when the decode logic programmed into the
DP83905 Network Interface Chip (NIC) detects an I/O or memory address for the
ZT 8995. Refer to the illustration "
Functional Diagram
" figure. Data is written to or read
from the ZT 8995 as required by the command decode and buffer control inside the
NIC.
Communications between the STD processor and the ZT 8995 are made via DMA
accesses to the NIC (I/O port mode, which is NE2000
plus compatible) or by the 16K
dual-ported (shared memory mode) packet RAM and I/O registers on the ZT 8995.
Normal communications between the processor and the adapter consist of remote DMA
access to the NIC (I/O mode) or by writing transmit frames to shared memory (shared
memory mode) and then initiating a packet. The network interface then performs a DMA
transfer of the frame data between the shared packet RAM and the network interface. In
the receive direction, the network interface performs a DMA transfer of received frames
to the packet RAM, and then interrupts the processor when the completed packet has
been received. Alternately, the processor does not have to be interrupted, but can poll
the network controller to determine if a packet has been received.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com