D. Specifications
69
The STD bus unit load reflects input current requirements at worst case conditions over
recommended supply voltage and ambient temperature ranges. An output rated at 60
unit loads can drive 60 STD bus cards having input rated at one unit load.
The "
STD Bus Loading, P Connector
" table includes load values for STD-80
connections. The "
STD Bus Loading, E Connector
" table includes load values for
STD 32 connections.
Note:
The ZT 8995 uses CMOS devices which have high and low input currents of
±10 µA.
STD Bus Loading, P Connector
ZT8995
+5 VDC
GND
DCPDN*
PIN (CIRCUIT SIDE)
OUTPUT DRIVE
INPUT LOAD
MNEMONIC
D7/A13 [1]
D6/A22 [1]
D5/A21 [1]
D4/A20 [1]
A15
A14
A13
A12
A11
A10
A9
A8
RD*
MEMRQ*
BHE
ALE*
STATUS 0*
BUSRQ*
INTRQ*
NMIRQ*
PBRESET*
INTRQ2* (CNTRL*)
PCI [3]
AUX GND
AUX-V
AUX GND
AUX+V
SYSRESET* [2]
CLOCK* [2]
PCO [3]
STATUS 1*
BUSAK*
INTAK*
WAITRQ*
WR*
IORQ*
IOEXP
INTRQ1*
A3
A2
A1
A0
A7
A6
A5
A4
D3/A19 [1]
D2/A18 [1]
D1/A17 [1]
D0/A16 [1]
+5 VDC
GND
VBAT (INTRQ4)
PIN (COMPONENT SIDE)
OUTPUT DRIVE
INPUT LOAD
MNEMONIC
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P42
P44
P46
P48
P50
P52
P56
P54 P53
P55
P47
P49
P51
P39
P41
P43
P45
P31
P33
P35
P37
P23
P25
P27
P29
P15
P17
P19
P21
P7
P9
P11
P13
P1
P3
P5
Notes:
[1] High order address bits multiplied over the data bus.
[2] SYSRESET* and CLOCK* are outputs in permanent master configuration and inputs in
[3] PCI is connected to PCO.
REQ indicates required connection.
temporary master configuration.
60
60
60
60
60
60
60
60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
60
60
60
60
1
1
1
60
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