PV152
2-17
PRO1200 CIRCUIT DESCRIPTION
CIRCUIT DESCRIPTION
The Scan Fail loop (SF0-SF1-SF2-SF3-SF4-SF5-SF6) passes
through two contacts of the deflection connectors and
two contacts of the connector on the Deflection Switch-
ing module. In the event that one of these yoke con-
nectors or Deflection Switching module is disconnected,
the projector will go into scan fail, terminating the EHT.
Note:
HDM is the midpoint of the two series connected
deflection MOSFETS. HDL is the common connection to
the three horizontal yoke windings, that supplies the
yokes with the +HTHD voltage, after passing through Q3
and the linearity coil.
TECHNICAL DESCRIPTION “CONTROLLER” 809-10453
Introduction.
The controller module can be divided into four blocks:
the RWI (Real World Interface), CTRL (Controller), ASIC
and PLL.
Each block has a typical function, but needs informa-
tion from the other blocks. These connections are real-
ized by the address / data bus or by “handshake” sig-
nals. Address and data are split by a GAL - ADEC (
A
ddress
DECoder).
The schematic diagram consists of 4 sheets: Sheet 1=Con-
troller, Sheet 2=ASIC+PLL, Sheet 3=RWI and Sheet 4=I/O
+ Power Supplies.
Real World Interface
The RWI is responsible for the communication with the
peripheral circuitry of the projector, particularly the PPM
(Pulse Position Modulated) commands. These commands
can come in via the IR receiver, coming straight from
the attached keypad, via the PC communication (RS232)
port or the RCVDS port.
This electronic part must be supplied from the +9V
SB
supply line, as it must be ready in stand-by to respond
to an ON command. The state of the switching transistor
Q23 (on the I/O) is determined by the
“SMPS”
line. This
is the output pin 11 of IC28, which is supplied from the
micro-controller IC19. Whether this line is high or low
at the moment the Main is supplied, depends on the DIP
switch position “Power ON/OFF” (S2, switch 4).
The data bus of the RWI micro-controller IC19 is con-
nected with the main controller IC2 via a bi-directional
buffer IC23.
The multiplexed address/data bus P0 of the
microcontroller drives the LEDs D30 - D37 and the DIP
switches via the buffer IC24 (74HCT573).
Watchdog - 9 Volt Watch
(Page 6-32 Sect. F-2)
The watchdog is built around IC25 pins 1 - 2 - 3 and
Q20 transistor. At switching on the projector, the +5VSB
is supplied to this circuit. As C68 is not charged at
switching on, the output pin 1 is high for a moment in
order to reset the microcontroller at pin 10 of IC19 (RST).
Pin 3 of IC25 is set at half the supply voltage. The
microcontroller triggers the watchdog via C67 in order
to keep capacitor C68 charged by conduction of Q20.
If the processor gets blocked, the level detector output
pin 1 becomes high and resets the controller as described
before. The watchdog has the task of restarting the con-
troller when it gets blocked.
Arcing in a CRT will temporarily short the +5V supply.
This can damage the microprocessor. For that reason,
the other level detector in IC25 monitors the 9V
(9VWATCH). The output of this detector is connected to
the
INT0
of the processor.
Controller (CTRL)
(Page 6-32)
The Controller is built around the chipset 68000 micro-
processor, 68230 and 68901. The chip 68230 and 68901
provide the in-/output bit (e.g. PLL-drive, I
2
C coinci-
dence...), the bus connection with the RWI, the serial
communication with the RCVDS and the interrupt-in-
puts.
The Gal IC7 is the address decoder; all I/O are memory
mapped. At the same time IC7 provides the DTACK (data
acknowledge) of the other components to the 68000.
The Gal IC8 provides for the interrupt management and
separates RD and WR from RD/WR.
The information adjusted by the user regarding the set-
tings of the different blocks (memory blocks) are stocked
in the E²PROM IC6.
The clock generator is built around IC1/XT1. The buff-
ered TXDRCV and RXDRCV are the communication lines
with the switcher / selector RCVDS800 or RCVDS05. The
RDY line (Ready line) informs the microprocessor on the
status of the switcher (powered up or powered down).
ASIC
(Page 6-34)
The ASIC IC17 integrates different functions and is cus-
tom made for this application. This chip is, with others,
responsible for the generation and synchronization of
the text that must be projected on request. The text or
pixel information is loaded by the controller into the
RAM IC18. Eight bytes are loaded into the RAM via the
ASIC during the HFB time. (The controller cannot start
up when there are no HFB pulses available from the ASIC).
When an external source is selected, the ASIC measures
the line and vertical frequencies and informs the main
processor if there are changes (change of resolution mode
or change of source).
The pixel clock, generated by the VCO of the PLL, is sent
