PV152
2-8
PRO1200 CIRCUIT DESCRIPTION
CIRCUIT DESCRIPTION
TECHNICAL DESCRIPTION “UN SYNC + VERT DEFL”
809-10456
(Page 6-9 Sect. B&C-9)
a) Vertical Oscillator
The principle of the oscillator is to determine the ap-
propriated charging current of the real oscillator, pro-
portional to the vertical frequency, by generating a stable
simulated vertical sawtooth.
We find two current sources Q38,and Q37 driven by the
output of the Miller integrator output pin 7 of IC16.
The minimum or initial charge current is determined by
R168. The capacitor C13 is charged up and discharged
when Q19 is driven on with the V Syn pulse. The sawtooth
is buffered and integrated (= average) and the obtained
voltage is compared with the level set by P1 (ADJUST-
MENT VERTICAL HOLD). The charging current is adapted
via R161 / D50 until both voltages at the input are
identical. When the feedback is stable, the two current
sources send current to two circuits:
1. Sawtooth simulator as explained above for vert.
autolock.
2. Second sawtooth oscillator for the V_ST signal.
With P1 we can adjust the average output voltage of
the integrator. The potentiometer must be adjusted in
order to obtain vertical lock, the frequency is irrelevant.
The sawtooth is buffered and feeds one potentiometers
in IC2. The VO0 output is buffered with Q27/28 and AC
coupled to the power amplifiers.
The linearity control is built around the diff. Amplifier
IC8, which receives at the non inverting input the V_PAR’
signal and at the other the adjusted V_PAR’. The output,
pin 14, is added to the V_ST signal in order to compress
or decompress the ramp at the top or bottom. The lin-
earity is controlled by a potentiometer in IC2.
The Vertical oscillator is synchronized as follows:
1)By means of the composite sync
(Page 6-9 Sect.A-3)
The composite video
(VID)
, composite sync
(CS)
or Hor
Sync
(HS)
is, at any time, applied to pin 2 of IC14, a
typical sync separator. The output pin 1 serves the digi-
tal PLL IC6 for all modes.
If D606 is in conduction (depends on the DC level of the
input signal) the video composite also passes on to Q2,
for serving the TDA2595. In this case D601 is blocked
and the output pin 1 of the LM1881 is not used.
The TDA2595 is used as sync separator for video com-
posite since its input is noise - integrating. In that
case the transistor Q596 is saturated and D601 is blocked.
If the sync input is HS or CS, then, the LM1881 is used
as sync separator since it has no integrator at the in-
put.
The composite sync output HS / CS, pin 1, is proceed-
ing to IC1 via a buffer Q2 (Q596 is not saturated then).
The output pin 9 of IC1 is providing composite sync
pulses which are now sent to the base of Q7 through the
Vert. Sync separator circuit, built around the OP AMP
IC9 with output pin 7. If we assume that the switcher
Q6 is conducting (see later), the negative pulses on the
collector of Q7 can trigger the vertical oscillator.
The oscillator can also be triggered by means of the ver-
tical pulses
V Sync,
which come straight from an BNC
input (via the differential input, at the base of Q4.
Note that an optional HDTV interface with tri-level sync
may be connected to the J7 connector.
2) By means of the vertical pulses VSync, if applied
separately
(Page 6-9 Sect. A-7)
These vertical pulses enter the board at contact 13 of
the J4A connector and are capacitively coupled to the
base of Q4.
The amplified negative pulses on the collector trigger
the oscillator now via D10 / D7.
To prevent triggering via Q7, the fet Q6 is now blocked
as follows:
Each time a VS pulse arrives on the base of Q4, capacitor
C23 is charged via D9 / Q4. Consequently, the gate of Q6
is low and Q6 is blocked, to disconnect the emitter of
Q7.
c) 4 x digital controlled potentiometer
(Page 6-9 Sect.
E-2)
The voltage or waveform, applied between
VRPx
and
VRNx,
the two extremities of a potentiometer
,
is adjustable in
128 steps through the remote control (I2C bus). The
output, or, the ‘slider’ voltage is available at
VOx
. The
corresponding pins are eg. VRP
1,
VRN
1
and VO
1.
We find
4
of such potentiometers
in one chip
, and there
are three of these chips on the subunit: IC1, IC2 and
IC3, which we will meet in the explanations hereafter.
The output waveform or voltage is controlled by the
SCL
