MOTIF XS6/MOTIF XS7/MOTIF XS8
76
SN74AHC1G14DCKR
(X5440A00)
Single Schmitt-Trigger lnverter Gate
AM26LS31CNSR
(XU996A00)
Quad Line Driver
LTC1694-1CS5
(X5367A00)
SMbus Accelerator
R5520H001B-T1-F
(X7569A00)
USB HIGH-SIDE POWER SW.
LTC1773EMS
(X3215A00)
DC-DC CONVERTER
I
TH
1
RUN/SS
2
SYNC/FCB
3
V
FB
4
GND
5
SW
10
SENSE–
9
V
IN
8
TG
7
BG
6
BURST
DEFEAT
0.4
μ
A
1.5
μ
A
0.6V
OSC
FREQ
SHIFT
0.8V REF
UVLO
TRIP = 2.5V
SYNC
DEFEAT
X
Y
Y = “0” ONLY WHEN X IN A CONSTANT “1”
SLOPE
COMP
3
SYNC/FCB
4
V
FB
2
RUN/SS
1
I
TH
8
V
IN
0.8V
SYNC
DEFEAT
0.22V
50mV
EN
SLEEP
0.4V
BURST
COMP
0.86V
OVDET
0.8V
EA
I
RCMP
I
COMP
UVLO
TRIP = 2.5V
SHUTDOWN
S
Q
R
Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI
SHOOT-THRU
9
SENSE–
7
TG
6
BG
10
SW
5
GND
1
5
2
3
4
Vcc
NC
SMBus 1
SMBus 2
GND
2
GND
4
SMBus2
5
SMBus1
1
Vcc
100uA
175uA
1,925mA
STANDBY
SLEW RATE
DETECTOR
+
-
CONTROL
LOGIC
CHANNEL TWO
(DUPLICATE OF CHANNEL ONE)
0.65V
V
REF
VOLTAGE
COMP
GATE
CONTROL
5
OUT
3
FLG
2
GND
4
IN
1
EN
CURRENT
LIMIT
UVLO
THERMAL
SHUTDOWN
FLAG
DELAY
1
5
2
3
4
EN
FLG
OUT
IN
GND
1
2
3
4
5
6
7
1A
1Y
1Z
2Z
2Y
2A
GND
ENABLE G
16
15
14
13
12
11
Vcc
4A
4Y
4Z
ENABLE G
3Z
3Y
8
9
10
3A
OUTPUTS
H= high level
L= low level
X= irrelevant
Z= high impedance (off)
ENABLES
INPUT
A
G
G
Y
Z
H
H
X
X
L
X
X
L
L
H
H
L
H
L
Z
L
H
L
H
Z
H
L
H
L
X
1
2
3
A
Vcc
Y
NC
4
5
GND