56
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
Appendix C:
Master UCF Listing
NET FMC2_HA16_N LOC = L27 | IOSTANDARD=LVCMOS18; # Bank 36
NET IO_25_VRP_36 LOC = M26 | IOSTANDARD=LVCMOS18; # Bank 36
NET IO_0_VRN_37 LOC = F21 | IOSTANDARD=LVCMOS18; # Bank 37
NET MGT_MOD_SPI_SCK LOC = A24 | IOSTANDARD=LVCMOS18; # Bank 37
NET MGT_MOD_SPI_D LOC = A25 | IOSTANDARD=LVCMOS18; # Bank 37
NET MGT_MOD_SPI_Q LOC = B22 | IOSTANDARD=LVCMOS18; # Bank 37
NET GTX_MOD_SPI_CS LOC = A22 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L3P_T0_DQS_37 LOC = A26 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L3N_T0_DQS_37 LOC = A27 | IOSTANDARD=LVCMOS18; # Bank 37
NET SA2_SDHOST_CMD LOC = C23 | IOSTANDARD=LVCMOS18; # Bank 37
NET SA2_SDHOST_D0 LOC = B23 | IOSTANDARD=LVCMOS18; # Bank 37
NET SA2_SDHOST_D1 LOC = B26 | IOSTANDARD=LVCMOS18; # Bank 37
NET SA2_SDHOST_D3 LOC = B27 | IOSTANDARD=LVCMOS18; # Bank 37
NET SA2_SDHOST_D2 LOC = C24 | IOSTANDARD=LVCMOS18; # Bank 37
NET SA2_SDHOST_CLK LOC = B24 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L7P_T1_37 LOC = E23 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L7N_T1_37 LOC = E24 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L8P_T1_37 LOC = F22 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L8N_T1_37 LOC = E22 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L9P_T1_DQS_37 LOC = F25 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L9N_T1_DQS_37 LOC = E25 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L10P_T1_37 LOC = D22 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L10N_T1_37 LOC = D23 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L11P_T1_SRCC_37 LOC = D25 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L11N_T1_SRCC_37 LOC = D26 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L12P_T1_MRCC_37 LOC = C25 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L12N_T1_MRCC_37 LOC = C26 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L13P_T2_MRCC_37 LOC = D27 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L13N_T2_MRCC_37 LOC = D28 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L14P_T2_SRCC_37 LOC = C28 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L14N_T2_SRCC_37 LOC = C29 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_GPIO_0 LOC = B28 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_GPIO_1 LOC = B29 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_GPIO_2 LOC = A31 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_GPIO_3 LOC = A32 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_TXD_0 LOC = A29 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_RXD_I LOC = A30 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_RTS_0_B LOC = C31 | IOSTANDARD=LVCMOS18; # Bank 37
NET USB_CTS_I_B LOC = B31 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L19P_T3_37 LOC = E30 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L19N_T3_VREF_37 LOC = D31 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L20P_T3_37 LOC = D30 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L20N_T3_37 LOC = C30 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L21P_T3_DQS_37 LOC = E27 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L21N_T3_DQS_37 LOC = E28 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L22P_T3_37 LOC = F29 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L22N_T3_37 LOC = E29 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L23P_T3_37 LOC = F26 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L23N_T3_37 LOC = F27 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L24P_T3_37 LOC = F30 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_L24N_T3_37 LOC = F31 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_25_VRP_37 LOC = F24 | IOSTANDARD=LVCMOS18; # Bank 37
NET IO_0_VRN_38 LOC = K18 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_0 LOC = C19 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_1 LOC = B19 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_2 LOC = A16 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_3 LOC = A15 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_4 LOC = A20 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_5 LOC = A19 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_6 LOC = B17 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_7 LOC = A17 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_8 LOC = B21 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_9 LOC = A21 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_10 LOC = C18 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_11 LOC = B18 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_12 LOC = D20 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_13 LOC = C20 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_14 LOC = F17 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_15 LOC = E17 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_16 LOC = D21 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_17 LOC = C21 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_18 LOC = D18 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_CTRL_19 LOC = D17 | IOSTANDARD=LVCMOS18; # Bank 38
NET IO_L11P_T1_SRCC_38 LOC = G19 | IOSTANDARD=LVCMOS18; # Bank 38
NET IO_L11N_T1_SRCC_38 LOC = F19 | IOSTANDARD=LVCMOS18; # Bank 38
NET LVDS_OSC_P LOC = E19 | IOSTANDARD=LVDS; # Bank 38
NET LVDS_OSC_N LOC = E18 | IOSTANDARD=LVDS; # Bank 38
NET CLK_DIFF_1_P LOC = H19 | IOSTANDARD=LVCMOS18; # Bank 38
NET CLK_DIFF_1_N LOC = G18 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_GCLK_P LOC = K19 | IOSTANDARD=LVCMOS18; # Bank 38
NET CM_GCLK_N LOC = J18 | IOSTANDARD=LVCMOS18; # Bank 38
