VC7203 GTX Transceiver Characterization Board
55
UG957 (v1.0) October 10, 2012
VC7203 Board UCF Listing
NET FMC2_LA27_P LOC = E33 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA27_N LOC = D33 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA28_P LOC = C33 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA28_N LOC = C34 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA18_CC_P LOC = D35 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA18_CC_N LOC = D36 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA17_CC_P LOC = C35 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA17_CC_N LOC = C36 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_CLK0_M2C_P LOC = E34 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_CLK0_M2C_N LOC = E35 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_CLK1_M2C_P LOC = D37 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_CLK1_M2C_N LOC = D38 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA29_P LOC = G32 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA29_N LOC = F32 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA30_P LOC = F36 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA30_N LOC = F37 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA31_P LOC = F34 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA31_N LOC = F35 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA32_P LOC = H33 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA32_N LOC = G33 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA33_P LOC = E37 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_LA33_N LOC = E38 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA07_P LOC = G36 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA07_N LOC = G37 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA08_P LOC = F39 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA08_N LOC = E39 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA09_P LOC = J37 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA09_N LOC = J38 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA10_P LOC = H38 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA10_N LOC = G38 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA11_P LOC = J36 | IOSTANDARD=LVCMOS18; # Bank 35
NET FMC2_HA11_N LOC = H36 | IOSTANDARD=LVCMOS18; # Bank 35
NET IO_25_VRP_35 LOC = G34 | IOSTANDARD=LVCMOS18; # Bank 35
NET IO_0_VRN_36 LOC = M23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB01_P LOC = H24 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB01_N LOC = G24 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB02_P LOC = J21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB02_N LOC = H21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB03_P LOC = H25 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB03_N LOC = H26 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB04_P LOC = G21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB04_N LOC = G22 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB05_P LOC = G26 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB05_N LOC = G27 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB07_P LOC = H23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB07_N LOC = G23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB08_P LOC = G28 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB08_N LOC = G29 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB09_P LOC = K28 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB09_N LOC = J28 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB10_P LOC = H28 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB10_N LOC = H29 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB11_P LOC = K27 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB11_N LOC = J27 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB06_CC_P LOC = K24 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB06_CC_N LOC = K25 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB00_CC_P LOC = J25 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB00_CC_N LOC = J26 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_CLK2_BIDIR_P LOC = M24 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_CLK2_BIDIR_N LOC = L24 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_CLK3_BIDIR_P LOC = K23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_CLK3_BIDIR_N LOC = J23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB12_P LOC = M22 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB12_N LOC = L22 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB13_P LOC = L25 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB13_N LOC = L26 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB14_P LOC = K22 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB14_N LOC = J22 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB15_P LOC = M21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB15_N LOC = L21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB16_P LOC = P21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HB16_N LOC = N21 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA12_P LOC = P25 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA12_N LOC = P26 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA13_P LOC = P22 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA13_N LOC = P23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA14_P LOC = N25 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA14_N LOC = N26 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA15_P LOC = N23 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA15_N LOC = N24 | IOSTANDARD=LVCMOS18; # Bank 36
NET FMC2_HA16_P LOC = M27 | IOSTANDARD=LVCMOS18; # Bank 36
