Xilinx VC7203, User Manual

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26 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
Chapter 1: VC7203 Board Features and Operation
USB-to-UART Bridge
Callout 21 , Figure 1-2 .
A USB-to-UART bridge (U34, Silicon Laboratories CP2103) is provided for serial
communication between a host computer and the FPGA over a USB cable. The USB
connector on the board is a mini-B receptacle (J79) and its pinout is shown in
Table 1-15 .
The CP2103 supports an IO voltage range of 1.8V to 3.3V. Xilinx UART IP is expected to be
implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four
signal pins:
• Transmit (TX)
• Receive (RX)
• Request to Send (RTS)
• Clear to Send (CTS)
Connections of these signals between the FPGA and the CP2103 are listed in Table 1-16 .
The bridge device also provides as many as 4 GPIO signals that can be defined by the user
for status and control information (
Table 1-17 ).
E8 118_REFCLK1_P 118 J86
E7 118_REFCLK1_N 118 J86
Table 1-14: GTX Transceiver Reference Clock Inputs (Cont’d)
U1 FPGA Pin Net Name Quad Connector
Table 1-15: USB Mini-B Receptacle Pin Assignments and Signals
J79 Pin Signal Name Description
1 VBUS
+5V into the CP2103 USB-to-UART bridge at U34.
Used to sense USB network connection.
2 USB_DATA_N Bidirectional differential serial data (N-side).
3 USB_DATA_P Bidirectional differential serial data (P-side).
4 GROUND Signal ground.
Table 1-16: FPGA to UART Connections
U1 FPGA Pin FPGA Function Net Name U34 Pin U34 Function
B31 RTS, output USB_CTS_I_B 22 CTS, input
C31 CTS, input USB_RTS_0_B 23 RTS, output
A30 TX, data out USB_RXD_I 24 RXD, data in
A29 RX, data in USB_TXD_0 25 TXD, data out