Xilinx VC7203, User Manual

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VC7203 GTX Transceiver Characterization Board www.xilinx.com 19
UG957 (v1.0) October 10, 2012
Detailed Description
interface. The VC7203 board also supplies UTIL_5V0, UTIL_3V3, UTIL_2V5 and
VCCO_HR input power to the clock module interface.
Table 1-9: SuperClock-2 FPGA I/O Mapping
U1 FPGA Pin Net Name J82 Pin
E12 CM_LVDS1_P 1
D12 CM_LVDS1_N 3
L12 CM_LVDS2_P 9
L11 CM_LVDS2_N 11
BA12 CM_LVDS3_P 17
BB12 CM_LVDS3_N 19
K19 CM_GCLK_P 25
J18 CM_GCLK_N 27
C19 CM_CTRL_0 61
B19 CM_CTRL_1 63
A16 CM_CTRL_2 65
A15 CM_CTRL_3 67
A20 CM_CTRL_4 69
A19 CM_CTRL_5 71
B17 CM_CTRL_6 73
A17 CM_CTRL_7 75
B21 CM_CTRL_8 77
A21 CM_CTRL_9 79
C18 CM_CTRL_10 81
B18 CM_CTRL_11 83
D20 CM_CTRL_12 85
C20 CM_CTRL_13 87
F17 CM_CTRL_14 89
E17 CM_CTRL_15 91
D21 CM_CTRL_16 93
C21 CM_CTRL_17 95
D18 CM_CTRL_18 97
D17 CM_CTRL_19 99
F20 CM_CTRL_20 101
E20 CM_CTRL_21 103
K17 CM_CTRL_22 105