50
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
Appendix C:
Master UCF Listing
NET FMC1_HB07_N LOC = AH36 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB08_P LOC = Y37 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB08_N LOC = AA37 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB09_P LOC = Y35 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB09_N LOC = AA36 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB10_P LOC = AB36 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB10_N LOC = AB37 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB11_P LOC = AA34 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB11_N LOC = AA35 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB06_CC_P LOC = AB31 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB06_CC_N LOC = AB32 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB00_CC_P LOC = AB33 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB00_CC_N LOC = AC33 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_CLK2_BIDIR_P LOC = AD32 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_CLK2_BIDIR_N LOC = AD33 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_CLK3_BIDIR_P LOC = AC34 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_CLK3_BIDIR_N LOC = AD35 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB12_P LOC = AE32 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB12_N LOC = AE33 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB13_P LOC = AF31 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB13_N LOC = AF32 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB14_P LOC = AE34 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB14_N LOC = AE35 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB15_P LOC = AE29 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB15_N LOC = AE30 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB16_P LOC = Y32 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HB16_N LOC = Y33 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA12_P LOC = AC31 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA12_N LOC = AD31 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA13_P LOC = AA31 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA13_N LOC = AA32 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA14_P LOC = AC30 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA14_N LOC = AD30 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA15_P LOC = AA29 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA15_N LOC = AA30 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA16_P LOC = AB29 | IOSTANDARD=LVCMOS18; # Bank 16
NET FMC1_HA16_N LOC = AC29 | IOSTANDARD=LVCMOS18; # Bank 16
NET IO_25_VRP_16 LOC = AB34 | IOSTANDARD=LVCMOS18; # Bank 16
NET IO_0_VRN_17 LOC = Y38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L1P_T0_17 LOC = AB41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L1N_T0_17 LOC = AB42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L2P_T0_17 LOC = W40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L2N_T0_17 LOC = Y40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L3P_T0_DQS_17 LOC = Y39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L3N_T0_DQS_17 LOC = AA39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L4P_T0_17 LOC = Y42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L4N_T0_17 LOC = AA42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L5P_T0_17 LOC = AB38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L5N_T0_17 LOC = AB39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L6P_T0_17 LOC = AA40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L6N_T0_VREF_17 LOC = AA41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L7P_T1_17 LOC = AC38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L7N_T1_17 LOC = AC39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L8P_T1_17 LOC = AD42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L8N_T1_17 LOC = AE42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L9P_T1_DQS_17 LOC = AD38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L9N_T1_DQS_17 LOC = AE38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L10P_T1_17 LOC = AC40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L10N_T1_17 LOC = AC41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L11P_T1_SRCC_17 LOC = AE39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L11N_T1_SRCC_17 LOC = AE40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L12P_T1_MRCC_17 LOC = AD40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L12N_T1_MRCC_17 LOC = AD41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L13P_T2_MRCC_17 LOC = AF39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L13N_T2_MRCC_17 LOC = AF40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L14P_T2_SRCC_17 LOC = AF41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L14N_T2_SRCC_17 LOC = AG41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L15P_T2_DQS_17 LOC = AG39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L15N_T2_DQS_17 LOC = AH39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L16P_T2_17 LOC = AF42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L16N_T2_17 LOC = AG42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L17P_T2_17 LOC = AG38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L17N_T2_17 LOC = AH38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L18P_T2_17 LOC = AJ38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L18N_T2_17 LOC = AK38 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L19P_T3_17 LOC = AK40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L19N_T3_VREF_17 LOC = AL40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L20P_T3_17 LOC = AH40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L20N_T3_17 LOC = AH41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L21P_T3_DQS_17 LOC = AL41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L21N_T3_DQS_17 LOC = AL42 | IOSTANDARD=LVCMOS18; # Bank 17
