VC7203 GTX Transceiver Characterization Board
47
UG957 (v1.0) October 10, 2012
Appendix C
Master UCF Listing
The VC7203 board master user constraints file (UCF) template provides for designs
targeting the VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board. Net names
in the constraints listed below correlate with net names on the VC7203 board schematic.
Users must identify the appropriate pins and replace the net names below with net names
in the user RTL. See
Constraints Guide
for more information.
VC7203 Board UCF Listing
NET IO_0_VRN_12 LOC = AN29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L1P_T0_AD0P_12 LOC = AY27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L1N_T0_AD0N_12 LOC = AY28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L2P_T0_AD8P_12 LOC = AU29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L2N_T0_AD8N_12 LOC = AV29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L3P_T0_DQS_AD1P_12 LOC = BA26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L3N_T0_DQS_AD1N_12 LOC = BA27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L4P_T0_12 LOC = BB28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L4N_T0_12 LOC = BB29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L5P_T0_AD9P_12 LOC = BB26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L5N_T0_AD9N_12 LOC = BB27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L6P_T0_12 LOC = AY29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L6N_T0_VREF_12 LOC = BA29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L7P_T1_AD2P_12 LOC = AW25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L7N_T1_AD2N_12 LOC = AW26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L8P_T1_AD10P_12 LOC = AR29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L8N_T1_AD10N_12 LOC = AT29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L9P_T1_DQS_AD3P_12 LOC = AV25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L9N_T1_DQS_AD3N_12 LOC = AV26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L10P_T1_AD11P_12 LOC = AW27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L10N_T1_AD11N_12 LOC = AW28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L11P_T1_SRCC_12 LOC = AU28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L11N_T1_SRCC_12 LOC = AV28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L12P_T1_MRCC_12 LOC = AU26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L12N_T1_MRCC_12 LOC = AU27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L13P_T2_MRCC_12 LOC = AR27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L13N_T2_MRCC_12 LOC = AT27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L14P_T2_SRCC_12 LOC = AP27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L14N_T2_SRCC_12 LOC = AR28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L15P_T2_DQS_12 LOC = AN28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L15N_T2_DQS_ADV_B_12 LOC = AP28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L16P_T2_A28_12 LOC = AT25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L16N_T2_A27_12 LOC = AT26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L17P_T2_A26_12 LOC = AP25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L17N_T2_A25_12 LOC = AR25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L18P_T2_A24_12 LOC = AN25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L18N_T2_A23_12 LOC = AN26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L19P_T3_A22_12 LOC = AM28 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L19N_T3_A21_VREF_12 LOC = AM29 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L20P_T3_A20_12 LOC = AK27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L20N_T3_A19_12 LOC = AL27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L21P_T3_DQS_12 LOC = AM26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L21N_T3_DQS_A18_12 LOC = AM27 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L22P_T3_A17_12 LOC = AK24 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L22N_T3_A16_12 LOC = AK25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L23P_T3_FOE_B_12 LOC = AL25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L23N_T3_FWE_B_12 LOC = AL26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L24P_T3_RS1_12 LOC = AJ25 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_L24N_T3_RS0_12 LOC = AJ26 | IOSTANDARD=LVCMOS18; # Bank 12
NET IO_25_VRP_12 LOC = AP26 | IOSTANDARD=LVCMOS18; # Bank 12
