Xilinx VC709, User Manual

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VC709 Evaluation Board www.xilinx.com 25
UG887 (v1.2.1) March 11, 2014
Feature Descriptions
Clock Generation
The VC709 board provides six clock sources for the FPGA. Table 1-7 lists the source devices
for each clock.
Table 1-8 lists the pin-to-pin connections from each clock source to the FPGA.
Table 1-7: VC709 Board Clock Sources
Clock Name
Clock
Source
Description
System clock U51
SiT9102 2.5V LVDS 200 MHz fixed frequency oscillator (Si Time)
See System Clock (SYSCLK_P and SYSCLK_N), page 26 .
User clock U34
Si570 3.3V LVDS I
2
C Programmable Oscillator, (
I
2
C address
0x5D
), 156.250 MHz
default (Silicon Labs).
See Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N), page 27 .
User SMA clock
(differential pair)
J31
USER_SMA_CLOCK_P (net name)
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N),
page 28 .
J32
USER_SMA_CLOCK_N (net name)
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N),
page 28 .
GTH SMA REF clock
(differential pair)
J25
SMA_MGT_REFCLK_C_P (net name)
See GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N),
page 28 .
J26
SMA_MGT_REFCLK_C_N (net name)
See GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N),
page 28 .
Jitter-attenuated clock U24
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs)
See Jitter-Attenuated Clock, page 29 .
Memory clock U13
SiT9122 2.5V LVDS 233.33
MHz fixed frequency oscillator (Si Time).
See Memory Clock (SYSCLK_233_P and SYSCLK_233_N), page 30 .
FPGA EMCC clock U40
SiT8103 LVCMOS single-ended, 80 MHz, fixed-frequency oscillator (Si Time). See
FPGA EMCC Clock, page 31 .
Table 1-8: Clock Connections, Source to FPGA
Clock Source Pin Net Name FPGA (U1) Pin
U51.5 SYSCLK_N G18
U51.4 SYSCLK_P H19
U34.5 USER_CLOCK_N AL34
U34.4 USER_CLOCK_P AK34
J26.1 SMA_MGT_REFCLK_N AK7
J25.1 SMA_MGT_REFCLK_P AK8
J32.1 USER_SMA_CLOCK_N AK32