Xilinx VC709, User Manual

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26 www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Chapter 1: VC709 Evaluation Board Features
System Clock (SYSCLK_P and SYSCLK_N)
[ Figure 1-2 , callout 5 ]
The VC709 board has an LVDS 200 MHz oscillator (U51) soldered onto the back side of the
board and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is
named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins H19 and G18
respectively.
• Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
• PPM frequency jitter: 50 ppm
• Differential output
The LVDS termination resistor R2, located within the FPGA via matrix on the bottom of the
board, is not populated. One possible I/O standard for the FPGA design clock input is:
NET "sysclk_p" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank 38
MRCC input
NET "sysclk_n" LOC = "G18" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.
Rterm R2 DNP
For more details, see the Si Time SiT9102 data sheet. The system clock circuit is shown in
Figure 1-7 .
J31.1 USER_SMA_CLOCK_P AJ32
U24.29 Si5324_OUT_N AD7
U24.28 Si5324_OUT_P AD8
U13.5 SYSCLK_233_N AY17
U13.4 SYSCLK_233_P AY18
U40.3 FPGA_EMCCLK AP37
Table 1-8: Clock Connections, Source to FPGA
Clock Source Pin Net Name FPGA (U1) Pin