Xilinx VC709, User Manual

Page: 10 / 100

10 www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Chapter 1: VC709 Evaluation Board Features
• JTAG using a type-A to micro-B USB cable for connecting the host PC to the VC709
board configuration port
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
Table 1-2 . The mode switches M2, M1, and M0 are on SW11 positions 3,
4, and 5 respectively as shown in Figure 1-3 .
Note:
To determine the FPGA type resident on the VC709 board, see the Virtex-7 VC709
Evaluation Kit Master Answer Record (AR 51901) .
The default mode setting is M[2:0] =
010
, which selects Master BPI at board power-on. See
Configuration Options, page 63 for detailed information about the mode switch SW11.
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470) [Ref 2] .
I/O Voltage Rails
There are 17 I/O banks available on the Virtex-7 device. Fourteen I/O banks are available
on the VC709 board, and banks 12, 16, and 18 are not used. The voltages applied to the
FPGA I/O banks used by the VC709 board are listed in
Table 1-3 .
X-Ref Target - Figure 1-3
Figure 1-3: SW11 Default Settings
Table 1-2: VC709 Board FPGA Configuration Modes
Configuration Mode
SW13 DIP Switch
Settings (M[2:0])
Bus Width CCLK Direction
Master BPI
010
x8, x16 Output
JTAG
101
x1 Not applicable
UG 88 7_c1_0 3 _0 83 112
1
OFF Po s ition = 0
ON Po s ition = 1
2 3 4 5
A25
A24 M2
M1 M0
Table 1-3: I/O Voltage Rails
FPGA (U1) Bank Power Supply Rail Net Name Voltage
Bank 0 VCC1V8_FPGA 1.8V
Bank 12 NOT USED 1.8V
Bank 13 VCC1V8_FPGA 1.8V
Bank 14 VCC1V8_FPGA 1.8V
Bank 15 VCC1V8_FPGA 1.8V
Bank 16 NOT USED 1.8V
Bank 17 VCC1V8_FPGA 1.8V
Bank 18 NOT USED 1.8V