Xilinx VC709, User Manual

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34 www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Chapter 1: VC709 Evaluation Board Features
For more information on the GTH transceivers see
7 Series FPGAs GTX/GTH Transceivers
User Guide (
UG476)
[Ref 5] .
PCI Express Endpoint Connectivity
[ Figure 1-2 , callout 11 ]
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application, 5.0 GT/s for a Gen2 application, and 8.0 GT/s for a Gen3 application.
The PCIe transmit and receive signal datapaths have a characteristic impedance of
85
Ω
±10%. The PCIe clock is routed as a 100
Ω
differential pair. The 7 series FPGAs GTH
transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX690T-2FFG1761C FPGA (-2 speed grade) included with the VC709 board
supports up to Gen3 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock circuit is shown in
Figure 1-14 .
GTHE2_CHANNEL_X1Y29 FMC2 HPC DP8
GTHE2_CHANNEL_X1Y28 FMC2 HPC DP9
MGTREFCLK0 NC
MGTREFCLK1 NC
MGT_BANK_118 GTHE2_CHANNEL_X1Y35 FMC1 HPC DP7
GTHE2_CHANNEL_X1Y34 FMC1 HPC DP6
GTHE2_CHANNEL_X1Y33 FMC1 HPC DP5
GTHE2_CHANNEL_X1Y32 FMC1 HPC DP4
MGTREFCLK0 FMC1 HPC GBT_CLK1
MGTREFCLK1 FMC2 HPC GBT_CLK0
MGT_BANK_119 GTHE2_CHANNEL_X1Y39 FMC1 HPC DP3
GTHE2_CHANNEL_X1Y38 FMC1 HPC DP2
GTHE2_CHANNEL_X1Y37 FMC1 HPC DP1
GTHE2_CHANNEL_X1Y36 FMC1 HPC DP0
MGTREFCLK0 NC
MGTREFCLK1 NC
Table 1-9: GTH Quad Connection Assignments (Cont’d)
Transceiver Bank Channel/Clock Connections