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VC709 Evaluation Board

UG887 (v1.2.1) March 11, 2014

Chapter 1:

VC709 Evaluation Board Features

Table 1-12

lists the PCIe edge connector connections for Quad 114.

MGTXRXP2_115_AA6

AA6

PCIE_RX1_P

B19

PETp1

GTHE2_CHANNEL_X1Y22

MGTXRXN2_115_AA5

AA5

PCIE_RX1_N

B20

PETn1

GTHE2_CHANNEL_X1Y22

MGTXTXP3_115_W2

PCIE_TX0_P

A16

PERp0

GTHE2_CHANNEL_X1Y23

MGTXTXN3_115_W1

PCIE_TX0_N

A17

PERn0

GTHE2_CHANNEL_X1Y23

MGTXRXP3_115_Y4

PCIE_RX0_P

B14

PETp0

GTHE2_CHANNEL_X1Y23

MGTXRXN3_115_Y3

PCIE_RX0_N

B15

PETn0

GTHE2_CHANNEL_X1Y23

MGTREFCLK0P_115_Y8

MGT_BANK_115

MGTREFCLK0N_115_Y7

MGT_BANK_115

MGTREFCLK1P_115_AB8

AB8

PCIE_CLK_Q0_N

A13

REFCLK-

MGT_BANK_115

MGTREFCLK1N_115_AB7

AB7

PCIE_CLK_Q0_P

A14

MGT_BANK_115

Table 1-11:

GTH Quad 115 PCIe Edge Connector Connections

(Cont’d)

Quad 115 Pin Name

FPGA

(U1) Pin

Net Name

PCIe Edge Connector

(P1)

FFG1761 Placement

Pin

Pin Name

Table 1-12:

GTH Quad 114 PCIe Edge Connector Connections

Quad 114 Pin Name

FPGA

(U1) Pin

Net Name

PCIe Edge Connector

(P1)

FFG1761 Placement

Pin

Pin Name

MGTXTXP0_114_AK4

AK4

PCIE_TX7_P

A47

PERp7

GTHE2_CHANNEL_X1Y16

MGTXTXN0_114_AK3

AK3

PCIE_TX7_N

A48

PERn7

GTHE2_CHANNEL_X1Y16

MGTXRXP0_114_AG6

AG6

PCIE_RX7_P

B45

PETp7

GTHE2_CHANNEL_X1Y16

MGTXRXN0_114_AG5

AG5

PCIE_RX7_N

B46

PETn7

GTHE2_CHANNEL_X1Y16

MGTXTXP1_114_AJ2

AJ2

PCIE_TX6_P

A43

PERp6

GTHE2_CHANNEL_X1Y17

MGTXTXN1_114_AJ1

AJ1

PCIE_TX6_N

A44

PERn6

GTHE2_CHANNEL_X1Y17

MGTXRXP1_114_AF4

AF4

PCIE_RX6_P

B41

PETp6

GTHE2_CHANNEL_X1Y17

MGTXRXN1_114_AF3

AF3

PCIE_RX6_N

B42

PETn6

GTHE2_CHANNEL_X1Y17

MGTXTXP2_114_AH4

AH4

PCIE_TX5_P

A39

PERp5

GTHE2_CHANNEL_X1Y18

MGTXTXN2_114_AH3

AH3

PCIE_TX5_N

A40

PERn5

GTHE2_CHANNEL_X1Y18

MGTXRXP2_114_AE6

AE6

PCIE_RX5_P

B37

PETp5

GTHE2_CHANNEL_X1Y18

MGTXRXN2_114_AE5

AE5

PCIE_RX5_N

B38

PETn5

GTHE2_CHANNEL_X1Y18

MGTXTXP3_114_AG2

AG2

PCIE_TX4_P

A35

PERp4

GTHE2_CHANNEL_X1Y19

MGTXTXN3_114_AG1

AG1

PCIE_TX4_N

A36

PERn4

GTHE2_CHANNEL_X1Y19

MGTXRXP3_114_AD4

AD4

PCIE_RX4_P

B33

PETp4

GTHE2_CHANNEL_X1Y19

MGTXRXN3_114_AD3

AD3

PCIE_RX4_N

B34

PETn4

GTHE2_CHANNEL_X1Y19

Summary of Contents for VC709

Page 1: ...VC709 Evaluation Board for the Virtex 7 FPGA User Guide UG887 v1 2 1 March 11 2014...

Page 2: ...ity for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Copyright 2013 2014 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Vivado Virtex Zynq and...

Page 3: ...rs 32 PCI Express Endpoint Connectivity 34 SFP SFP Module Connectors 39 USB to UART Bridge 42 I2C Bus 43 Status LEDs 45 User I O 45 Switches 49 VITA 57 1 FMC1 HPC Connector Partially Populated 51 Powe...

Page 4: ...Environmental 95 Temperature 95 Humidity 95 Operating Voltage 95 Appendix F Additional Resources Xilinx Resources 97 Solution Centers 97 References 97 Appendix G Regulatory and Compliance Information...

Page 5: ...FMC is provided See VC709 Board Features for a complete list of features The details for each feature are described in Feature Descriptions page 7 Additional Information See Appendix F Additional Res...

Page 6: ...r power good FPGA INIT FPGA DONE User I O User LEDs eight GPIO User pushbuttons five directional CPU reset pushbutton User DIP switch 8 pole GPIO Switches Power on off slide switch FPGA_PROG_B pushbut...

Page 7: ...t the current revision of the board X Ref Target Figure 1 1 Figure 1 1 VC709 Board Block Diagram HPC FMC Connector 4 GB DDR3 Memory SODIMM 1 KB EEPROM I2C I2C Bus Switch DIP Switch SW11 Config and Fla...

Page 8: ...AXC7VX690T 2FFG1761C with cooling fan XC7VX690T 2FFG1761C 2 J1 J3 Two DDR3 SODIMM memories 4 GB each Micron MT8KTF51264HZ 1G9E1 10 14 3 U3 BPI parallel NOR flash memory 1 Gb Micron Numonyx PC28F00AG18...

Page 9: ...ser pushbuttons active High E Switch TL3301EP100QG 25 18 SW2 User DIP switch active High 8 pole C and K SDA08H1SBD 25 19 SW8 SW9 CPU RESET FPGA PROG pushbuttons E Switch TL3301EP100QG 25 7 20 SW11 Con...

Page 10: ...or full details on configuring the FPGA see 7 Series FPGAs Configuration User Guide UG470 Ref 2 I O Voltage Rails There are 17 I O banks available on the Virtex 7 device Fourteen I O banks are availab...

Page 11: ...REF is provided for data interface banks 37 39 31 and 33 Any interface connected to these banks that requires a reference voltage must use this FPGA voltage reference The connections between the DDR3...

Page 12: ...2 79 BA2 N14 DDR3_A_D0 5 DQ0 N13 DDR3_A_D1 7 DQ1 L14 DDR3_A_D2 15 DQ2 M14 DDR3_A_D3 17 DQ3 M12 DDR3_A_D4 4 DQ4 N15 DDR3_A_D5 6 DQ5 M11 DDR3_A_D6 16 DQ6 L12 DDR3_A_D7 18 DQ7 K14 DDR3_A_D8 21 DQ8 K13 DD...

Page 13: ...32 B23 DDR3_A_D33 131 DQ33 B27 DDR3_A_D34 141 DQ34 B26 DDR3_A_D35 143 DQ35 A22 DDR3_A_D36 130 DQ36 B22 DDR3_A_D37 132 DQ37 A25 DDR3_A_D38 140 DQ38 C24 DDR3_A_D39 142 DQ39 E24 DDR3_A_D40 147 DQ40 D23 D...

Page 14: ...5 DDR3_A_DM1 28 DM1 F12 DDR3_A_DM2 46 DM2 A14 DDR3_A_DM3 63 DM3 C23 DDR3_A_DM4 136 DM4 D25 DDR3_A_DM5 153 DM5 C31 DDR3_A_DM6 170 DM6 F31 DDR3_A_DM7 187 DM7 M16 DDR3_A_DQS0_N 10 DQS0_N N16 DDR3_A_DQS0_...

Page 15: ...DR3_A_CAS_B 115 CAS_B H20 DDR3_A_ODT0 116 ODT0 H18 DDR3_A_ODT1 120 ODT1 J17 DDR3_A_S0_B 114 S0_B J20 DDR3_A_S1_B 121 S1_B P18 DDR3_A_RESET_B 30 RESET_B G17 DDR3_A_TEMP_EVENT_B 198 EVENT_B Table 1 5 DD...

Page 16: ...Q1 AR22 DDR3_B_D2 15 DQ2 AR23 DDR3_B_D3 17 DQ3 AN23 DDR3_B_D4 4 DQ4 AM23 DDR3_B_D5 6 DQ5 AN21 DDR3_B_D6 16 DQ6 AP21 DDR3_B_D7 18 DQ7 AK23 DDR3_B_D8 21 DQ8 AJ23 DDR3_B_D9 23 DQ9 AL21 DDR3_B_D10 33 DQ10...

Page 17: ...4 BB13 DDR3_B_D35 143 DQ35 AW12 DDR3_B_D36 130 DQ36 AY13 DDR3_B_D37 132 DQ37 AY12 DDR3_B_D38 140 DQ38 BA12 DDR3_B_D39 142 DQ39 AU12 DDR3_B_D40 147 DQ40 AU13 DDR3_B_D41 149 DQ41 AT12 DDR3_B_D42 157 DQ4...

Page 18: ...M3 63 DM3 BB12 DDR3_B_DM4 136 DM4 AV15 DDR3_B_DM5 153 DM5 AK12 DDR3_B_DM6 170 DM6 AP13 DDR3_B_DM7 187 DM7 AP22 DDR3_B_DQS0_N 10 DQS0_N AP23 DDR3_B_DQS0_P 12 DQS0_P AK22 DDR3_B_DQS1_N 27 DQS1_N AJ22 DD...

Page 19: ...64 pin BGA Part number PC28F00AG18FE Numonyx Supply voltage 1 8V Datapath width 16 bits 26 address lines and 7 control signals Data rate Up to 80 MHz The linear BPI flash memory can synchronously con...

Page 20: ...y appropriately setting the DIP switch SW11 The connections between the BPI flash memory and the FPGA are listed in Table 1 6 Table 1 6 BPI Flash Memory Connections to the FPGA FPGA U1 Pin Net Name BP...

Page 21: ...emory on the VC709 board For more details see the Micron Semiconductor PC28F00AG18FE data sheet NA NC H1 A27 AM36 FLASH_D0 F2 DQ0 AN36 FLASH_D1 E2 DQ1 AJ36 FLASH_D2 G3 DQ2 AJ37 FLASH_D3 E4 DQ3 AK37 FL...

Page 22: ...A24 FLASH_A24 A25 FLASH_A25 A26 NC A27 VCC2 VCCQ1 VCCQ2 VCCQ3 VPP VCC1 FLASH_D0_R DQ0 FLASH_D1_R DQ1 FLASH_D2_R DQ2 FLASH_D3_R DQ3 FLASH_D4_R DQ4 FLASH_D5_R DQ5 FLASH_D6_R DQ6 FLASH_D7_R DQ7 FLASH_D8...

Page 23: ...tch is in a normally closed state and transitions to an open state when an FMC mezzanine card is attached Switch U27 adds an attached FMC mezzanine card to the FPGAs JTAG chain as determined by the FM...

Page 24: ...com VC709 Evaluation Board UG887 v1 2 1 March 11 2014 Chapter 1 VC709 Evaluation Board Features The JTAG circuit details are shown in Figure 1 6 X Ref Target Figure 1 6 Figure 1 6 JTAG Circuit UG855_...

Page 25: ...LOCK_N page 28 J32 USER_SMA_CLOCK_N net name See User SMA Clock USER_SMA_CLOCK_P and USER_SMA_CLOCK_N page 28 GTH SMA REF clock differential pair J25 SMA_MGT_REFCLK_C_P net name See GTH SMA Clock SMA_...

Page 26: ...M frequency jitter 50 ppm Differential output The LVDS termination resistor R2 located within the FPGA via matrix on the bottom of the board is not populated One possible I O standard for the FPGA des...

Page 27: ...o an output frequency of 156 250 MHz User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface Power cycling the VC709 board reverts the user clo...

Page 28: ...1 9 GTH SMA Clock SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N Figure 1 2 callout 8 The VC709 board includes a pair of SMA connectors for a GTH clock wired to GTH Quad bank 113 This differential clock has si...

Page 29: ...PGA U1 pin AW33 for jitter attenuation The jitter attenuated clock Si5324_OUT_C_P Si5324_OUT_C_N is then routed as a reference clock to GTH Quad 113 inputs MGTREFCLK0P FPGA U1 pin AH8 and MGTREFCLK0N...

Page 30: ...the FPGA via matrix on the bottom of the board and is not populated X Ref Target Figure 1 11 Figure 1 11 Jitter Attenuated Clock UG887_c1_11_090612 R16 4 7K 5 SI5324_VCC Si5324C C GM Clock Multiplier...

Page 31: ...stem clock circuit is shown in Figure 1 12 FPGA EMCC Clock Note There is no Figure 1 2 callout for this clock The VC709 board has a LVCMOS 80 MHz oscillator U40 soldered onto the board and wired to th...

Page 32: ...escribed as Quads The reference clock for a Quad can be sourced from the Quad above or Quad below the GTH Quad of interest There are six GTH Quads on the VC709 board with connectivity as shown here Qu...

Page 33: ...channel and clock connection assignments Table 1 9 GTH Quad Connection Assignments Transceiver Bank Channel Clock Connections MGT_BANK_113 GTHE2_CHANNEL_X1Y15 SFP SFP 4 GTHE2_CHANNEL_X1Y14 SFP SFP 3 G...

Page 34: ...FFG1761C FPGA 2 speed grade included with the VC709 board supports up to Gen3 x8 The PCIe clock is input from the edge connector It is AC coupled to the FPGA through the MGTREFCLK1 pins of Quad 115 PC...

Page 35: ...RSNT_X8 J49 1 3 5 2 4 6 Table 1 10 PCIe Edge Connector Connections Net Name FPGA U1 Pin PCIe Edge Connector P1 Function FFG1761 Placement Pin Name PCIE_RX0_P Y4 B14 PETp0 IntegratedEndpointblock recei...

Page 36: ...ointblock transmit pair GTHE2_CHANNEL_X1Y23 PCIE_TX1_P AA2 A21 PERp1 IntegratedEndpointblock transmit pair GTHE2_CHANNEL_X1Y22 PCIE_TX1_N AA1 A22 PERn1 IntegratedEndpointblock transmit pair GTHE2_CHAN...

Page 37: ...U1 FPGA Bank13 Pin AV33 PCIE_PERST_B AV35 A11 PERST IntegratedEndpointblock reset signal U1 FPGA Bank13 Pin AV35 Table 1 10 PCIe Edge Connector Connections Cont d Net Name FPGA U1 Pin PCIe Edge Conne...

Page 38: ...4 PCIe Edge Connector Connections Quad 114 Pin Name FPGA U1 Pin Net Name PCIe Edge Connector P1 FFG1761 Placement Pin Pin Name MGTXTXP0_114_AK4 AK4 PCIE_TX7_P A47 PERp7 GTHE2_CHANNEL_X1Y16 MGTXTXN0_11...

Page 39: ...ports four small form factor pluggable SFP connector and cage assemblies P2 P5 that accept SFP or SFP modules Figure 1 16 shows an example of the SFP module connector circuitry replicated for each mod...

Page 40: ...2 1 3 4 5 6 7 8 9 10 SFP1_TX_FAULT SFP1_TX_DISABLE SFP1_MOD_DETECT SFP1_RS0 SFP1_RS1 SFP1_LOS NC NC SFP1_TX_FAULT_LS SFP1_TX_DISABLE_LS SFP1_MOD_DETECT_LS SFP1_RS0_LS SFP1_RS1_LS SFP1_LOS_LS SFP1_VCCR...

Page 41: ...X_N AJ6 SFP4_RX_P 13 RD_P AJ5 SFP4_RX_N 12 RD_N Table 1 14 SFP Module Control and Status XCVX690T U1 Pin Net Name SFP Module Pin Number Pin Name SFP Module 1 P3 Y38 SFP1_TX_FAULT 2 TX_FAULT AB42 SFP1_...

Page 42: ...X Receive RX Request to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers for the host computer These drivers permit the CP2103GM USB to UART bridge to app...

Page 43: ...P3 SFP2 P2 SFP3 P4 and SFP4 P5 are addressed through a secondary PCA9546A 1 to 4 channel I2C bus switch U14 The VC709 board I2C bus topology is shown in Figure 1 17 Table 1 15 USB Connector J17 Pin A...

Page 44: ...Bus Addresses I2C Bus I2C Switch Position I2C Address PCA9548 NA 0b1110100 USER_CLK_SDL SCL 0 0b1011101 FMC1_HPC_IIC_SDA SCL 1 0bxxxxx00 NOT USED 2 NOT USED EEPROM_IIC_SDA SCL 3 0b1010100 PCA9546 SFP...

Page 45: ...user pushbuttons and reset switch callout 17 GPIO_SW_ NESWC SW3 SW4 SW5 SW7 SW6 CPU_RESET SW8 8 position user DIP switch callout 18 GPIO_DIP_SW 7 0 SW2 Table 1 18 Status LEDs Reference Designator Sign...

Page 46: ...1 18 User LEDs GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 2 1 2 1 DS9 R154 49 9 1 10W 1 GND LED GRN SMT 2 1 2 1 DS8 R153 49 9 1 10W 1 LED GRN SMT 2 1 2 1...

Page 47: ...CC1V8 R39 4 7K 1 10W 5 TL3301EF100QG P1 P3 4 1 1 2 3 GPIO_SW_C 2 P2 P4 Pushbutton SW4 GND VCC1V8 R37 4 7K 1 10W 5 TL3301EF100QG P1 P3 4 1 1 2 3 GPIO_SW_E 2 P2 P4 Pushbutton SW5 GND UG887_c1_18_090612...

Page 48: ...1 R46 4 7K 1 10W 5 2 1 R48 4 7K 1 10W 5 2 1 R53 4 7K 1 10W 5 2 1 R51 4 7K 1 10W 5 2 1 R50 4 7K 1 10W 5 2 1 R52 4 7K 1 10W 5 2 1 R49 4 7K 1 10W 5 2 1 R47 4 7K 1 10W 5 GND UG887_c1_19_011013 Table 1 19...

Page 49: ...PGA reconfiguration The FPGA_PROG_B signal is connected to FPGA U1 pin AJ11 See 7 Series FPGAs Configuration User Guide UG470 Ref 2 for further details on configuring the 7 series FPGAs Figure 1 21 sh...

Page 50: ...illuminates when the VC709 board 12V power is on See Power Management page 56 for details on the onboard power system Caution Do NOT plug a PC ATX power supply 6 pin connector into J18 on the VC709 bo...

Page 51: ...of an FMC HPC connector provides pins for up to 160 single ended or 80 differential user defined signals 10 GTH transceivers 2 GTH clocks 4 differential clocks 159 ground and 15 power connections The...

Page 52: ...VITA 57 1 FMC HPC J35 Connections to FPGA U1 J35 FMC HPC Pin Schematic Net Name U1 FPGA Pin J64 FMC HPC Pin Schematic Net Name U1 FPGA Pin A2 FMC1_HPC_DP1_M2C_P C6 B1 NC NA A3 FMC1_HPC_DP1_M2C_N C5 B...

Page 53: ...P R42 C18 FMC1_HPC_LA14_P N39 D15 FMC1_HPC_LA09_N P42 C19 FMC1_HPC_LA14_N N40 D17 FMC1_HPC_LA13_P H39 C22 FMC1_HPC_LA18_CC_P M32 D18 FMC1_HPC_LA13_N G39 C23 FMC1_HPC_LA18_CC_N L32 D20 FMC1_HPC_LA17_CC...

Page 54: ...29 F22 FMC1_HPC_HB02_P K28 E24 FMC1_HPC_HB05_P K27 F23 FMC1_HPC_HB02_N J28 E25 FMC1_HPC_HB05_N J27 F25 FMC1_HPC_HB04_P H24 E27 FMC1_HPC_HB09_P H23 F26 FMC1_HPC_HB04_N G24 E28 FMC1_HPC_HB09_N G23 F28 F...

Page 55: ...FMC1_HPC_LA21_N N29 G30 FMC1_HPC_LA29_P T29 H28 FMC1_HPC_LA24_P R30 G31 FMC1_HPC_LA29_N T30 H29 FMC1_HPC_LA24_N P31 G33 FMC1_HPC_LA31_P M28 H31 FMC1_HPC_LA28_P L29 G34 FMC1_HPC_LA31_N M29 H32 FMC1_HPC...

Page 56: ...MC1_HPC_HB01_N H29 K25 FMC1_HPC_HB00_CC_P J25 J27 FMC1_HPC_HB07_P G26 K26 FMC1_HPC_HB00_CC_N J26 J28 FMC1_HPC_HB07_N G27 K28 FMC1_HPC_HB06_CC_P K23 J30 FMC1_HPC_HB11_P K22 K29 FMC1_HPC_HB06_CC_N J23 J...

Page 57: ...Switching Module VoutA VCCAUX1 8V at 10A 47 VCC3V3 Switching Regulator 5 0V at 1 5A Max LMZ12002 U36 45 Linear Regulator XADC_VCC 1 7V 2V at 300mA REF3012 U35 27 Switching Regulator 0 75V at 3A Max TP...

Page 58: ...8D210W VOUT A U21 of adjustable switching regulator dual 10A 0 6V to 3 6V VCC2V5_FPGA 2 50V 52 PTD08D210W VOUT B of adjustable switching regulator dual 10A 0 6V to 3 6V VCC1V5_FPGA 1 50V 52 PTD08D210W...

Page 59: ...ail is no longer deemed good The controller internally OR s these PG conditions together and drives an output PG pin high only if all active rail PG states are good The On and Off Delay and rise and f...

Page 60: ...275 30 5 10 1 1 725 9 5 84 3 Rail 3 MGTAVCC 1 0 9 0 85 10 4 35 4 1 45 9 5 84 4 Rail 4 MGTAVTT 1 2 1 08 1 02 15 4 25 4 1 38 9 5 84 Notes 1 The values defined in these columns are the voltage current an...

Page 61: ...ull SM_FAN_PWM high to turn the fan on More information about the power system components used by the VC709 board is available from the Texas Instrument digital power website Documentation describing...

Page 62: ...s supported A user provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines Figur...

Page 63: ...GPIO_0 XADC_GPIO_2 XADC_GPIO_1 XADC_GPIO_3 J19 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 GND XADC_AGND XADC_AGND XADC_VCC5V0 VADJ Table 1 25 XADC Header J19 Pinout Net Name J19 Pin Number Des...

Page 64: ...figuration and the FPGA To obtain the fastest configuration speed an external 80 MHz oscillator is wired to the EMCCLK pin of the FPGA This allows users to create bitstreams that configure the FPGA ov...

Page 65: ...A 26 1 U3 P28F00AG18FE 1Gb Flash Memory TCK TMS TDI TDO Bank 0 VCCO 1 8V CCLK INIT_B M 2 0 DONE PROG_B U1 FPGA SW9 Bank 15 VCCO 1 8V Bank 14 VCCO 1 8V FWE_B FOE_B ADV_B RS1 RS0 A 26 25 A 23 16 A 15 0...

Page 66: ...66 www xilinx com VC709 Evaluation Board UG887 v1 2 1 March 11 2014 Chapter 1 VC709 Evaluation Board Features...

Page 67: ...gs are shown in Figure A 1 and details are listed in Table A 1 X Ref Target Figure A 1 Figure A 1 SW2 Default Settings Table A 1 SW2 Default Switch Settings Position Function Default 1 GPIO_DIP_SW0 Of...

Page 68: ...SW11 Default Switch Settings Position Function Default 1 FLASH_A25 A25 Off 2 FLASH_A24 A24 Off 3 FPGA_M2 M0 Off 4 FPGA_M1 M1 On 5 FPGA_M0 M3 Off UG887_aA_02_083012 1 OFF Position 0 ON Position 1 2 3 4...

Page 69: ...M_P DP2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND D...

Page 70: ...70 www xilinx com VC709 Evaluation Board UG887 v1 2 1 March 11 2014 Appendix B VITA 57 1 FMC Connector Pinouts...

Page 71: ...rts GPIO_LED_4_LS set_property IOSTANDARD LVCMOS18 get_ports GPIO_LED_4_LS set_property PACKAGE_PIN AU34 get_ports SI5324_INT_ALM_LS set_property IOSTANDARD LVCMOS18 get_ports SI5324_INT_ALM_LS set_pr...

Page 72: ...ACKAGE_PIN AK37 get_ports FLASH_D4 set_property IOSTANDARD LVCMOS18 get_ports FLASH_D4 set_property PACKAGE_PIN AL37 get_ports FLASH_D5 set_property IOSTANDARD LVCMOS18 get_ports FLASH_D5 set_property...

Page 73: ...OS18 get_ports FLASH_A7 set_property PACKAGE_PIN AG29 get_ports FLASH_A6 set_property IOSTANDARD LVCMOS18 get_ports FLASH_A6 set_property PACKAGE_PIN AK28 get_ports FLASH_A5 set_property IOSTANDARD LV...

Page 74: ...AY39 get_ports PMBUS_DATA_LS set_property IOSTANDARD LVCMOS18 get_ports PMBUS_DATA_LS set_property PACKAGE_PIN AW37 get_ports PMBUS_CLK_LS set_property IOSTANDARD LVCMOS18 get_ports PMBUS_CLK_LS set_p...

Page 75: ...operty PACKAGE_PIN AA41 get_ports SFP3_TX_FAULT_LS set_property IOSTANDARD LVCMOS18 get_ports SFP3_TX_FAULT_LS set_property PACKAGE_PIN AC38 get_ports SFP3_TX_DISABLE_LS_B set_property IOSTANDARD LVCM...

Page 76: ...ports FMC1_HPC_LA06_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_LA06_N set_property PACKAGE_PIN M42 get_ports FMC1_HPC_LA03_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_LA03_P set_p...

Page 77: ...STL15 get_ports DDR3_B_DM6 set_property PACKAGE_PIN AM13 get_ports DDR3_B_D60 set_property IOSTANDARD SSTL15 get_ports DDR3_B_D60 set_property PACKAGE_PIN AN13 get_ports DDR3_B_D61 set_property IOSTAN...

Page 78: ...erty PACKAGE_PIN BB14 get_ports DDR3_B_D34 set_property IOSTANDARD SSTL15 get_ports DDR3_B_D34 set_property PACKAGE_PIN BB13 get_ports DDR3_B_D35 set_property IOSTANDARD SSTL15 get_ports DDR3_B_D35 se...

Page 79: ...orts DDR3_B_CKE1 set_property PACKAGE_PIN AW17 get_ports DDR3_B_CKE0 set_property IOSTANDARD SSTL15 get_ports DDR3_B_CKE0 set_property PACKAGE_PIN AU19 get_ports DDR3_B_WE_B set_property IOSTANDARD SS...

Page 80: ...orts DDR3_B_D3 set_property IOSTANDARD SSTL15 get_ports DDR3_B_D3 set_property PACKAGE_PIN AR22 get_ports DDR3_B_D2 set_property IOSTANDARD SSTL15 get_ports DDR3_B_D2 set_property PACKAGE_PIN AT22 get...

Page 81: ...LA28_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_LA28_N set_property PACKAGE_PIN J31 get_ports FMC1_HPC_LA27_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_LA27_P set_property PACKAGE...

Page 82: ...A20_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_LA20_P set_property PACKAGE_PIN Y30 get_ports FMC1_HPC_LA20_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_LA20_N set_property PACKAGE_...

Page 83: ..._ports FMC1_HPC_HA21_N set_property PACKAGE_PIN G32 get_ports FMC1_HPC_HA05_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_HA05_P set_property PACKAGE_PIN F32 get_ports FMC1_HPC_HA05_N set_prop...

Page 84: ...roperty IOSTANDARD LVCMOS18 get_ports FMC1_HPC_HB07_N set_property PACKAGE_PIN H23 get_ports FMC1_HPC_HB09_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_HB09_P set_property PACKAGE_PIN G23 get...

Page 85: ..._HB13_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_HB13_P set_property PACKAGE_PIN P26 get_ports FMC1_HPC_HB13_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HPC_HB13_N set_property PACKAG...

Page 86: ...DR3_A_D51 set_property IOSTANDARD SSTL15 get_ports DDR3_A_D51 set_property PACKAGE_PIN B28 get_ports DDR3_A_DQS6_P set_property IOSTANDARD DIFF_SSTL15 get_ports DDR3_A_DQS6_P set_property PACKAGE_PIN...

Page 87: ...perty PACKAGE_PIN C18 get_ports DDR3_A_A7 set_property IOSTANDARD SSTL15 get_ports DDR3_A_A7 set_property PACKAGE_PIN D20 get_ports DDR3_A_A6 set_property IOSTANDARD SSTL15 get_ports DDR3_A_A6 set_pro...

Page 88: ...KAGE_PIN A14 get_ports DDR3_A_DM3 set_property IOSTANDARD SSTL15 get_ports DDR3_A_DM3 set_property PACKAGE_PIN C15 get_ports DDR3_A_DQS3_P set_property IOSTANDARD SSTL15 get_ports DDR3_A_DQS3_P set_pr...

Page 89: ...D SSTL15 get_ports DDR3_A_D13 set_property PACKAGE_PIN L12 get_ports DDR3_A_D7 set_property IOSTANDARD SSTL15 get_ports DDR3_A_D7 set_property PACKAGE_PIN M14 get_ports DDR3_A_D3 set_property IOSTANDA...

Page 90: ...get_ports PCIE_RX0_P set_property PACKAGE_PIN W1 get_ports PCIE_TX0_N set_property PACKAGE_PIN Y3 get_ports PCIE_RX0_N set_property PACKAGE_PIN AA2 get_ports PCIE_TX1_P set_property PACKAGE_PIN AA6 ge...

Page 91: ...C1_HPC_DP4_C2M_N set_property PACKAGE_PIN H7 get_ports FMC1_HPC_DP4_M2C_N set_property PACKAGE_PIN B4 get_ports FMC1_HPC_DP3_C2M_P set_property PACKAGE_PIN A6 get_ports FMC1_HPC_DP3_M2C_P set_property...

Page 92: ...92 www xilinx com VC709 Evaluation Board UG887 v1 2 1 March 11 2014 Appendix C Master XDC Listing...

Page 93: ...five screws Re attach the PCIe bracket with two screws 2 Power down the host computer and remove the AC power cord from the PC 3 Open the PC chassis following the instructions provided with the PC 4 S...

Page 94: ...e bundle mating 4 pin 1 x 4 peripheral power connector Caution Do NOT plug a PC ATX power supply 6 pin connector into J18 on the VC709 board The ATX 6 pin connector has a different pinout than J18 Con...

Page 95: ...cations Dimensions Height 5 5 inch 14 0 cm Length 10 5 inch 26 7 cm Note The VC709 board height exceeds the standard 4 376 inch 11 15 cm height of a PCI Express card Environmental Temperature Operatin...

Page 96: ...96 www xilinx com VC709 Evaluation Board UG887 v1 2 1 March 11 2014 Appendix E Board Specifications...

Page 97: ...PGA VC709 Connectivity Kit Virtex 7 FPGA VC709 Connectivity Kit Documentation website Virtex 7 VC709 Evaluation Kit Master Answer Record AR 51901 These Xilinx documents and sites provide supplemental...

Page 98: ...Semiconductor Numonyx PC28F00AG18FE 13 Si Time SiT9102 SiT9122 14 Silicon Labs Si570 Si5324C CP2103GM VCP Drivers 15 Texas Instruments UCD9248PFC PTD08A010W PTD08A020W PTD08D021W LMZ12002 TL1962ADC TP...

Page 99: ...line Directives 2006 95 EC Low Voltage Directive LVD 2004 108 EC Electromagnetic Compatibility EMC Directive Standards EN standards are maintained by the European Committee for Electrotechnical Standa...

Page 100: ...This product complies with Directive 2002 96 EC on waste electrical and electronic equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic produ...

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