Xilinx VC709, User Manual

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VC709 Evaluation Board www.xilinx.com 27
UG887 (v1.2.1) March 11, 2014
Feature Descriptions
Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N)
[ Figure 1-2 , callout 6 ]
The VC709 board has a programmable low-jitter 3.3V differential oscillator (U34)
connected to the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and
USER_CLOCK_N clock signal pair are connected to FPGA U1 pins AK34 and AL34
respectively. On power-up, the user clock defaults to an output frequency of 156.250 MHz.
User applications can change the output frequency within the range of 10 MHz to
810 MHz through an I
2
C interface. Power cycling the VC709 board reverts the user clock to
its default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz – 810 MHz)
• PPM frequency jitter: 50 ppm
• Differential output
• I
2
C address
0x5D
1. For more details, see the Silicon Labs Si570 data sheet . The user clock circuit is shown in
Figure 1-8 .
Note:
In
Figure 1-8 ,
USER_CLOCK_N and USER_CLOCK_P are differential clock signals.
X-Ref Target - Figure 1-7
Figure 1-7: System Clock Source
UG 88 7_c1_07_01101 3