32
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Chapter 1:
VC709 Evaluation Board Features
GTH Transceivers
[
, callout
The VC709 board provides access to 22 GTH transceivers:
•
Eight of the GTH transceivers are wired to the PCI Express x8 endpoint edge
connector (P1) fingers.
•
Ten of the GTH transceivers are wired to the FMC HPC connector (J35).
•
Four of the GTH transceivers are wired to the four SFP/SFP+ connectors (P2, P3, P4,
P5).
The GTH transceivers in 7 series FPGAs are grouped into four channels described as
Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below
the GTH Quad of interest. There are six GTH Quads on the VC709 board with connectivity
as shown here:
•
Quad 113:
•
MGTREFCLK0 - Si5324 jitter attenuator
•
MGTREFCLK1 - SMA clock
•
Contains 4 GTH transceivers with one each allocated to SFP 1 through 4
•
Quad 114:
•
MGTREFCLK0 - No clock
•
MGTREFCLK1 - No clock
•
Contains 4 GTH transceivers for PCIe lanes 4–7
•
Quad 115:
•
MGTREFCLK0 - No clock
•
MGTREFCLK1 - PCIe edge connector clock
X-Ref Target - Figure 1-13
Figure 1-13:
FPGA External EMCC Clock
OE
1
1
2
2
4
3
FPGA EMCCLK
S
IT
8
10
3
S
IT
8
10
3
AC-2
3
-1
8
E-
8
0.0000Y
8
0.00000MHZ
50PPM
VCC1V
8
to FPGA U1
pin AP
3
7
GND
C
8
0.1UF
10V
X5R
U40
GND
VCC
OUT
UG
88
7_c1_1
3
_05221
3
