Xilinx VC709, User Manual

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VC709 Evaluation Board www.xilinx.com 19
UG887 (v1.2.1) March 11, 2014
Feature Descriptions
The VC709 DDR3 SODIMM interfaces adhere to the constraints guidelines documented in
the DDR3 Design Guidelines section of
7 Series FPGAs Memory Interface Solutions
User Guide (UG586) [Ref 3] . The VC709 DDR3 SODIMM interfaces are 40
Ω
impedance
implementations. Other memory interface details are also available in 7 Series FPGAs
Memory Interface Solutions User Guide (UG586) [Ref 3] and 7 Series FPGAs Memory Resources
User Guide (UG473) [Ref 4] .
Linear BPI Flash Memory
[ Figure 1-2 , callout 3 ]
The linear BPI flash memory located at U3 provides 128 MB of nonvolatile storage that can
be used for configuration or software storage. The data, address, and control signals are
connected to the FPGA. The BPI flash memory device is packaged in a 64-pin BGA.
• Part number: PC28F00AG18FE (Numonyx)
• Supply voltage: 1.8V
• Datapath width: 16 bits (26 address lines and 7 control signals)
• Data rate: Up to 80 MHz
The linear BPI flash memory can synchronously configure the FPGA in Master BPI mode at
the 80 MHz data rate supported by the PC28F00AG18FE flash memory by using a
configuration bitstream generated with BitGen options for synchronous configuration. The
AN14 DDR3_B_DQS7_N 186 DQS7_N
AN15 DDR3_B_DQS7_P 188 DQS7_P
AU17 DDR3_B_CLK0_N 101 CK0_P
AT17 DDR3_B_CLK0_P 103 CK0_N
AV18 DDR3_B_CLK1_N 102 CK1_P
AU18 DDR3_B_CLK1_P 104 CK1_N
AW17 DDR3_B_CKE0 73 CKE0
AW18 DDR3_B_CKE1 74 CKE1
AV19 DDR3_B_RAS_B 110 RAS_B
AU19 DDR3_B_WE_B 113 WE_B
AT20 DDR3_B_CAS_B 115 CAS_B
AT16 DDR3_B_ODT0 116 ODT0
AW16 DDR3_B_ODT1 120 ODT1
AV16 DDR3_B_S0_B 114 S0_B
AT19 DDR3_B_S1_B 121 S1_B
BB19 DDR3_B_RESET_B 30 RESET_B
AU16 DDR3_B_TEMP_EVENT_B 198 EVENT_B
Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA (Cont’d)
XCVX690T (U1) Pin Net Name
SODIMM Memory J3
Pin Number Pin Name