Xilinx VC709, User Manual

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VC709 Evaluation Board www.xilinx.com 31
UG887 (v1.2.1) March 11, 2014
Feature Descriptions
One possible I/O standard for the FPGA design clock input is:
NET "sysclk_233_p" LOC = "AY18" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank
32 MRCC input
NET "sysclk_233_n" LOC = "AY17" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.
Rterm R43 DNP
3. For more details, see the
Si Time
SiT9122 data sheet. The system clock circuit is shown
in Figure 1-12 .
FPGA EMCC Clock
Note:
There is no
Figure 1-2 callout for this clock.
The VC709 board has a LVCMOS 80 MHz oscillator (U40) soldered onto the board and
wired to the FPGA EMCCLK clock input pin AP37 on bank 14. This 80 MHz single-ended
signal is named FPGA_EMCCLK.
• Oscillator: Si Time SIT8103AC-23-18E-80.0000Y
• PPM frequency jitter: 50 ppm
• Single-ended 1.8V LVCMOS output
The FPGA EMCC external configuration clock circuit is shown in Figure 1-13 .
X-Ref Target - Figure 1-12
Figure 1-12: Memory Clock Source
UG 88 7_c1_12_01101 3