Xilinx VC709, User Manual

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30 www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Chapter 1: VC709 Evaluation Board Features
2.
See the
Silicon Labs Si5324 data sheet for more information on this device.
Memory Clock (SYSCLK_233_P and SYSCLK_233_N)
[ Figure 1-2 , callout 27 ]
The VC709 board has a LVDS 233.3333 MHz oscillator (U13) soldered onto the back side of
the board and wired to an FPGA MRCC clock input on bank 32. This 233.3333 MHz signal
pair is named SYSCLK_233_P and SYSCLK_233_N. The P and N signals are connected to
FPGA U1 pins AY18 and AY17 respectively.
• Oscillator: Si Time SIT9122AC-2D3-25E233.333333 (233.3333 MHz)
• PPM frequency jitter: 50 ppm
• Differential output
The LVDS termination resistor R43 is located within the FPGA via matrix on the bottom of
the board, and is not populated.
X-Ref Target - Figure 1-11
Figure 1-11: Jitter-Attenuated Clock
UG 88 7_c1_11_090612
R16
4.7K
Ω
5%
S I5 3 24_VCC
S i5 3 24C-C-GM
Clock M u ltiplier/
Jitter Atten ua tor
VDD 3
GND
XB
XA
NC5
3 2
6
3 0
29
2 8
U24
CKOUT1_N
7
33
CKOUT1_P
C 3 1
0.1
μ
F 25V
X5R
C 3 2
0.1
μ
F 25V
X5R
S I5 3 26_XTAL_XA
GND2
GND1
XB
XA
X6
114.2 8 5 MHz
20 ppm
S I5 3 26_OUT_C_N
S I5 3 26_OUT_C_P
S I5 3 26_OUT_N
S I5 3 26_OUT_P
S I5 3 26_XTAL_XB
GND
NC4
2
1
3
4
C 33
0.1
μ
F 25V
X5R
C 3 4
0.1
μ
F 25V
X5R
REC_CLOCK_P
REC_CLOCK_N
REC_CLOCK_C_P
REC_CLOCK_C_N
16
17
R167
100
Ω
CKIN1_P
CKIN1_N
NC
NC
12
1 3
CKIN2_P
CKIN2_N
10
5
VDD2
VDD1
14
NC 3
9
NC2
2
NC1
NC
NC
NC
NC
NC
3 5
3 4
NC
NC
CKOUT2_P
CKOUT2_N
S I5 3 26_INT_ALM 3
NC 4
NC 11
NC 15
NC 1 8
19
20
S I5 3 26_R S T 1
21
3 1
GND2
9
GND1
3 1
A2_ SS
3 1
A1
24
A0
22 S I5 3 26_ S CL
S CL
2 3
S I5 3 26_ S DA
S DA_ S DO
27
NC
S DI
3 6
CMODE
GND
GND4
GND 3
LOL
RATE1
RATE0
C2B
INT_C1B
C S _CA
R S T_B
3 7
GNDPAD