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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Appendix E:
Rx Elastic Buffer Specifications
R
SGMII Fabric Rx Elastic Buffer
Figure E-2
illustrates the alternative FPGA fabric Rx Elastic Buffer depth and thresholds in
Virtex-II Pro, Virtex-4 FX and Virtex-5 LXT device families. Each FIFO word corresponds to
a single character of data (equivalent to a single byte of data following 8B10B decoding).
This buffer can optionally be used to replace the Rx Elastic Buffers of the RocketIO (see
“Receiver Elastic Buffer Implementations” in Chapter 8
).
The shaded area of
Figure E-2
represents the usable buffer availability for the duration of
frame reception.
•
If the buffer is filling during frame reception, there are 122-66 = 56 FIFO locations
available before the buffer reaches the overflow mark.
•
If the buffer is emptying during reception, then there are 62-6 = 56 FIFO locations
available before the buffer reaches the underflow mark.
Note that this analysis assumes the buffer is approximately at the half-full level at the start
of the frame reception. As illustrated, there are two locations of uncertainty, above and
below the exact half-full mark of 64. This is as a result of the clock correction decision, and
is based across an asynchronous boundary.
Because there is a worst-case scenario of one clock edge difference every 5000 clock
periods, the maximum number of clock cycles (bytes) that can exist in a single frame
passing through the buffer before an error occurs is:
5000 x 56 = 280000 bytes
Table E-2
translates this into maximum frame size at different Ethernet speeds. At SGMII
speeds lower than 1 Gbps, performance is diminished because bytes are repeated multiple
times (see
“Designing with Client-side GMII for the SGMII Standard” in Chapter 5
).
Figure E-2:
Elastic Buffer Size for all RocketIO families
12
8
66
122 - Overflow M
a
rk
6 - Underflow M
a
rk
S
GMII FPGA F
ab
ric
Rx El
as
tic B
u
ffer
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