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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 8:
SGMII / Dynamic Standards Switching with RocketIO Transceivers
R
(see the next section). However, there are logical implementations where this can be
reliable and has the benefit of lower logic utilization.
The Requirement for the FPGA Fabric Rx Elastic Buffer
Figure 8-1
illustrates a simplified diagram of a common situation where the core, in SGMII
mode, is interfaced to an external PHY device. Separate oscillator sources are used for the
FPGA and the external PHY. The Ethernet specification uses clock sources with a tolerance
of 100ppm. In
Figure 8-1
, the clock source for the PHY is slightly faster than the clock
source to the FPGA. For this reason, during frame reception, the receiver elastic buffer
(shown here as implemented in the RocketIO) starts to fill.
Following frame reception, in the interframe gap period, idles are removed from the
received data stream to return the Rx Elastic Buffer to half-full occupancy. This is
performed by the clock correction circuitry (see the RocketIO User Guide for the targeted
device).
Analysis
Assuming separate clock sources, each of tolerance 100 ppm, the maximum frequency
difference between the two devices can be 200 ppm. It can be shown that this translates
into a full clock period difference every 5000 clock periods.
Relating this to an Ethernet frame, there will be a single byte of difference every 5000 bytes
of received frame data, and this will cause the Rx Elastic Buffer to either fill or empty by an
occupancy of one.
The maximum Ethernet frame size (non-jumbo) is 1522 bytes for a VLAN frame.
•
At 1 Gbps operation, this translates into 1522 clock cycles.
•
At 100 Mbps operation, this translates into 15220 clock cycles (as each byte is repeated
10 times).
•
At 10 Mbps operation, this translates into 152200 clock cycles (as each byte is repeated
100 times).
Figure 8-1:
SGMII Implementation using Separate Clock Sources
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
RocketIO
Rx
El
as
tic
B
u
ffer
TXP/TXN
RXP/RXN
Twisted
Copper
Pair
S
GMII Link
10 BASE-T
100BASE-T
1000BASE-T
PHY
FPGA
100ppm
125MHz -100ppm
