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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 7:
1000BASE-X with RocketIO Transceivers
R
Virtex-5 FXT Devices
Figure 7-8
illustrates sharing clock resources across multiple instantiations of the core
when using Virtex-5 RocketIO GTX transceivers.
The example design can be generated to connect either a single instance of the core or
connect a pair of core instances to the transceiver pair present in a GTX tile.
Figure 7-8
illustrates two instantiations of the block level, and each block level contains a pair of
cores, consequently illustrating clock sharing between a total of four cores.
Additional cores can be added by continuing to instantiate extra block level modules.
Share the
brefclk_p
and
brefclk_n
differential clock pair. See the
Virtex-5 RocketIO
GTX Transceiver User Guide
for more information.
To provide the FPGA fabric clocks for all core instances, select a
REFCLKOUT
port from any
GTX transceiver and route this to a single DCM. The
CLK0
(125MHz) and
CLKDV
(62.5MHz) outputs from this DCM, placed onto global clock routing using a BUFGs, can be
shared across all core instances and GTX transceivers as illustrated.
